It's been a while since the last update so I wanted to give some news on how things are going with work towards the next release.
I've spent a lot of time working on getting the HLE audio code working on the Media Engine. I've been making steady progress, but it's been taking longer than I initially expected. Fortunately, I'm very close to getting all of the audio processing moved over to the ME - in fact I believe I have just one significant bug left to fix.
The issue seems to be a very odd synchronisation bug which causes the emulator to lock up when running the audio processing asynchronously. As with many of these types of bugs, it's proving quite hard to track down because as soon as I change the code to debug the problem, the issue goes away. A true Heisenbug :(
What's particularly annoying is that the bug is stopping me from measuring how much of a difference running the audio code on the ME makes. Hopefully I'll be able to fix the bug over the Christmas break and be able to publish some timings over the new year.
As part of this work, I've also been writing a general-purpose 'job manager', which coordinates batches of work between the main CPU and the ME. The idea is to build on top of J.F.'s MediaEngine.prx to provide a simple interface for queing up and dispatching work asynchronously. When a job is added to the queue, a flag indicates whether the job is suitable for running on the ME, or whether it should just be run asynchronously on the main CPU instead.
Initially just the audio processing will run through the job manager on the ME, but eventually it should be possible run other pieces of work asynchronously too. I'm hoping that it will eventually be possible to move parts of the HLE graphics processing to run asynchronously too, but I need to investigate things a bit more first. That's a job for future releases however.
Anyway, that's all for now. I'm off to eat mince pies and watch The Great Escape on tv. Merry Christmas everyone :)
-StrmnNrmn
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350 comments:
«Oldest ‹Older 201 – 350 of 350OMG just freaking update the blog it's not that hard Strmnnrmn. seriously update it already, it's been like forever, so seriously just update.GOD!
sorry if i seem really really rude, it's just there cant be much of an excuse for not updating for this long. it has been 4 months getting closer to 5 since the last update, i know he is doing this for free and i thank him, so don't lecture me on how i should be thankful. also i know he has a life, but nobody goes on a 4 almost 5 month vacation. and for all we know Wally could be a complete lier, i mean nobody really knows weather or not he is actually working with Strmnnrmn, aside from a few people saying that he is. and the whole R-14 Beta thing is, yes, an update, but it's not from Strmnnrmn himself. so we really don't know do we. until i get an update from strmnnrmn i wont believe it.or untill someone actually proves it.
PLEASE JUST UPDATE IT'LL ONLY TAKE LIKE 4 MINUETS, ANE EVERYONE WILL BE SO MUCH HAPPIER.
if he doesn't update by MAY im sorry, it's not like i want it to happen, but i'v also gotta say that this project is probably dead.
well, our favorite programmer seems dead. it's a pity...
if i had up a blog and it was in this situation, i'd update it every week or so..
4 months is way to long to not update. I'm losing interest coming here.
well i dont mind if he takes long cause NON of my games work (the best wrestling games were on n64 *HINT*) but i still respect strmnnrmn hey what can i do
Everyone respects him, but it's not like he will come back and all your "not working" games will be fixed. (Especially the wrestling games which is currently the last priority. No one but you likes them.)
Chances are that although he has extraordinary coding skills, he would rather play his xbox360 and waste his time. Not trying to be pesimistic, but 90% of coding projects that have been abandoned for over 3months do not get updated ever again. ITS BEEN 5 MONTHS!
I used to check this blog every day now I check it every 3-4days.
Sad, Just sad.
very sad
u_u
I sure hope so, i want new Daedalus :P
wow well i posted that previous one at the wrong time. i just think its dead though. damn and this is the one i actually wait for...
austinQPT um im sure there are quite a lot of people that would want the wrestling games on daedalus and plus finding the bug that causes wrestling games not to load will also help out on other games with similar loading problems
I also loved the wrestling games on N64, there are a lot more wrestling fans then you think. Hint, my username.
2/10000
more than 2 buddy just because you dont like wrestling games isnt my problem i know there's a game on n64 that u would want working (or you was still in pampers when n64 came out) again why do you even care in the first place its my opinion i and i QUOTE "I" would love to see these games playable and like i said in my last post it could lead to other non loading games think of it as a positive and not in a 4 year old brain
if everyone wanted them working, then more people would be complaining. only strmnnrmn would know if it would fix other games, so obviously if he hasn't fixed it by now then he feals it isn't worth the time to fix. pampers...wth..? I personally think more people wood rather see paper mario working, but even before that they'd rather see faster speed than better compatibility.
I dont get it.
who approves all the comments then?
if it is you Strmnnrmn, why not just leave a 10 word long post like , 'time off, will be back soon'
or just let us know its over, and someone else could (try) to pick up from where you left off
oooh...seems they are auto approved now
well that sucks!
yea they have been thats why they allow us to go so off topic lols..
@ AustinQPT, The reason not many ppl arent complaining about wrestling games is because there more of a demand for other games like Mario games and other good ones like 007 and Zelda. Im sure once he gets some of the goods ones going good some of the wrestling games might work. There are also a lot of wrestling fans that dont know or care about games or PSP emulators.
As many have said before: thanks for the good work! I'm going to buy a PSP very soon, but I love the old N64 games, so I'm certainly going to run Daedalus :)
As far as I can see, there hasn't been a status update since december. How's everything going? Are you near to releasing R14?
i need ta get me a PSP Slim. :/
i use my samsung Q1 ultra to play n64 games at full speed it cost me alot but go to my profile to find out what i did to get it.
@ AustinQPT
dude if u had read my comments earlier, around post 180, you would have seen that i use a parogram for windows called Project 64, it is a very good n64 emulator for pc and runs all games i have tried, at full speed. all you need to buy is a n64 controller, and a n64 to usb plug and you can play the games. the program is also completely free. which is definately an added bonus.
...samsung q1 ultra is a tablet umpc that runs windows xp... i use pj64 on it build 17 cuz i donate... yes it is full speed on mp psp sized pc =) btw 90% of the ppl who kno about daedalus know about pj64...
@ AustinQPT
sry dude i thought you were saying that the emulator that u were using on your pc was expencive, not the computer itself. and i just thought that the 10% of ppl that didn't know about pj64 would like to.
lol alright
just currious if theres going to be a release anytime soon we miss you bro :P
Hi, Strmnnrmn. I just wanted to thank you because of all the work you have done. And I ask you not to listen to all these comments asking for a new Release. If you want to publish a new release, then do it because you want to. I think that nobody can ask you for anything given that you have never asked us for anything, too. See you;)
Why not ask for an update or a release? You can't expect people not asking for... some of us have been following the project since very early releases (some from the begining) and we visit the blog everyday hoping for an update or some news about if the show goes on or not...
I had the "honor" to make the first post on this final thread hoping to hear a lot from Deadalus on 2008. I still hope so ;)
I also want to hear from Daedalus, and I visit the blog every day (more than once)and I would like to download a new update, but I think that we can't ask Strmnrm continuously for an update. At least, this is my point of view.
@Josep
Don't misunderstand me, i also think Strmnnrmn is in his full right not to post anything. The only thing i say is that you can't expect people not asking for...
After all this time following this project you get to feel a very little part of it as you see it grow & change and now it's like a father a bit worried bout how his son is doing ;)
Cheers
PD: ets català? :)
common strmnnrmn, throw us a bone, at least tell us your progress and such please!
.......................time of death Monday, December 24, 2007....
everyone who is complaining about StrmnNrmn`s work and his break shall do it better, or at least have a look on his source, to see how hard his FREE work is!
I still count on you, StrmnNrmn!
I like your emulator as it is, and I'm alwas happy again, when I see a new entry in your blog^^
I'm also very proud that so many guys are agreeing with me;)
You deserved your break->use it:T
Jeje, sí :P
even if it doesn't get updated ever again it IS legendary! I will remember the name StrmnNrmn the rest of my life, and I've already said his name prob around a thousand times when telling my friends of his accomplishments.
Very Ture! Strmnnrmn is a legend for getting the emulator this far, even if he doesnt come back youve got plenty of games to fiddle around with
so, Cheers to you Strmnnrmn
Well I highly appreciate what he has done so far. He has done so much more than most of us could ever dream of doing, and for that he has my utmost respect. I just hope he updates his blog soon as it has been a little while, even if it was just to tell us that he has dropped the project, or if he has not had time to update the project, we would understand. We would all just like to know what is happening at the moment. Any news is good news.
Thanks,
Glenn.
Think people - a good artist will do most of his work in silence. I believe there will be an update by July and there will probably be significant improvements. My personal feeling is that he's put so much work into this and he would tell us if it was over - silence is not an answer, it's just that, silence. So relax - I'm 99.999999 percent sure that he will emerge sometime - don't wait with baited breath to hear from him let it be a surprise and just check the sight once in a while - it will come. This is not over - strmnnrmn has friends in good places and he is or has probably all ready formed a team to help in the project, I think we will all be surprised!
"everyone who is complaining about StrmnNrmn`s work" nobody is complaining about his work, we're just tearing our hair out for another release, it's like once you get a taste of chocolate you want more, and everybody likes chocolate right? well most of us anyhow.
Agentsmith made a good point, if it was over, I'm sure he world have said something.
please come back ^^
Nearly been half a year since an update...
You know...there was a point in time, probably around December through February, where I checked this blog DAILY and HOURLY...hoping for an update. I had to give up. I've now been coming back every 2 weeks or so, hoping that in my absence he would have released the update, or just a blog update in the least. But still nothing. Its really disappointing =[. Although I beat Mario 64 with no sound haha. Pretty fun, but I still wanna do it with all the "HEYAAA"s and "WHOA"s you know =]
But yeah, cmon NRMN...I don't care what you post, just give us SOMETHING.
I have 117 stars on Mario 64. i forgot where to find the last 3. they're somewhere in the castle i know. yea, having fluent sound would be really nice to beat the game with. i check this blog like every week. no updates still :(
dead in my opinion. the original Daedalus on the PC also just died without explanation
i really hope its not true :(
'64 had the best console games, it would be so awesome if most of them worked properly on the psp. that'd be the best. i hope someone continues the project
If it's dead then that Icon contest was a waste of time, feel sorry for the winner not being able to have his pic in Daedalus.
I'm sure someone will continue it, if it really is dead. I feel sorry for the winner, too.
Settle down guys! Shit happens in life. Even if it is over for Nrmn, Don't look down upon it. He dedicated so much of his time to you guys, and all you can do is bitch and moan about it.
Well said, braden!
http://rapidshare.com/files/117660868/DaedalusR14.zip.html
is that real billy?
that better not be a scam..
@ braden
We're not really bitching and moaning everyones entitled to their comment.
Even if we are that's not nearly as worse as some of the people kissing up to strmnnrmn here
'he deserves a break'
Considering the rate at updates and releases in the past he takes breaks from daedalus all the time.
@ billy
That's random is this leaked ? Or maybe fake
It's got the winner of the icon contest pics in it.
@ popopola
I put it on my PSP and it didn't brick so it's worth a try, unless it's got a virus on it :P
huh? PSPs can't get viruses!!
@swish
can you actually run it? tell us what happens.
Check http://www.Myspace.com/DaedalusCompatibility
for a compatibility liast of working games on this leaked version of Daedalus R14
PSP's can't get a Virus but you have to download it to your computer first right, and it could have a virus on it that effects your computer.
From what i've tried on that leaked version my PSP just kept on freezing maybe because it needs a lot more work. After freezing once my PSP wouldn't turn back on until i plugged in the adapter even thou the battery had 17% left on it.
when it comes up with like a blue screen thing on the top of the screen keep pressing [] square, and i hope you guys appreciate what strmn has done so far even tho it is outdated
@ Billy.
dude i think it's totally cool what u did, releasing that beta, even if Strmnnrmn wouldn't like it, because if this blog is done with, and DAEDALUS is dead, then Strmnnrmn needs to take 2 seconds out of his 6 mont vacation to tell us. and if he can't be bothered to do that, than we should at least have the latest version. Even if it es Beta. thanks again.
@Braden
dude i understand what u mean by what u said, but you have to remember that Strmnnrmn has taken a break a really long half of a year break. i think it's about time he updated. even, sadly, if it is to tell us that the project is over.
@strmnnrmn
sory if i sound like im really rude, but those are the facts. i still very much appreciate what you are/were doing, and im sorry if something in your life went south and you feel that you need to stop work on this, or whatever the reason may be. thank you.
I appreciate what Strmn's done. At least he's proven that N64 is possible to emulate on the PSP. Wasn't that the point in the first place?
I tried out the beta. It's definitely not worth keeping, but the font looks cool. I tried copying the font from this beta to R13 but it didn't work. :(
i bet if someone (smarter than all of us in this field) looked at it, he might be able to change some configurations in the code, and enable it to work. but i doubt it.
on another note QJ.net is saying that Wally has also released this same thing, and i looked at that compatibility myspace page and i saw that super mario 64 was supposed to run at full speed, but when i tryed it with 3 different USA roms, and 1 EURO rom, it always froze up at the part with the "press square [] to hide all" that thing. afte about 3 or 4 of those it would display some text down at the bottom of the page saying like "rom is entering eeprom, unable to handle dil.ip-j,and then it would say Autio Buffer, ore something like that, and disp a number like 3789 or 4725 around those.
if anyone knows what that means can you tell me, or if it has to be a certain kind of Super Mario 64 rom or something. please.
oh, as a side not (i would do it myself but im buisy) can someone try naming their super mario 64 rom , with the same name as the picture for the preview image. i hope that maby R14 Beta is like coded to run a rom with a certain name. hopefully.
tks
no it wouldnt work and yea wally gave me the beata yesterday then i posted it on here then he posted it on another site that i frogot of.
About Mario 64 on this beta, load a saved state. it works but the controls don't operate in gameplay. Without using any controls, i noticed that the game is slower. I turned on the audio and it was gapping a lot..like it was in R9. Rush 2 works perfectly, but lags more frames than R13.
CaptainMorgan4 posted his own release of R14 on http://www.strmnnrmn.com/
check it out it works flawlessly, but i didn't see any significant frame rate difference. I'm actually getting 1 less frame per second than r13. Ive only tried SSB
Shortcut to file: http://rapidshare.de/files/39534167/CPM4.rar.html
enjoy :)
hey guys, check this out:
http://pspupdates.qj.net/Unnofficial-Daedalus-R14-Beta-released-Nintendo-64-Emulator-for-PSP/pg/49/aid/120535
qj.net isn't always 100% accurate with their info., but, at the very least, it's exciting to think about the possibility of Strmnnrmn being back on the dev. scene... plus, we finally have a public beta build of r14 :)
sorry, that wasn't the entire address:
http://pspupdates.qj.net/
Unnofficial-Daedalus-R14-Beta-
released-Nintendo-64-Emulator-
for-PSP/pg/49/aid/120535
enjoy!
@John
The Myspace page isn't updating because the Beta Versions aren't providing a large enough change in speed or compatibility, so all those results were from R13.
I read it on a bulletin
Wow those mince pies must be delicious
OMG i just got timemachins working and i tried out the 1.50 Daedalus R14 Beta that capton Morgan released, it's beautiful. the audio is running with a very minimal impact on frame rate, but the audio still sound sketchy, like it did before. a little bit better though, but still almost no impact on frame rate that i can tell and it is so much stabler than the other one. if anyone has a slim and wants to run this you should definitely get time machine on your psp. and if you don't have the 3.60 PSAR(i didn't have it) then you can easily find a download on the internet, just check it for viruses. and remember most people want to help you not hurt you so i wouldn't worry too much about viruses. also for time machine, if any of you were wondering what the msip.bin is, it is on the memory stick that you used for pandoras batt, or desp del cem. it doesn't matter which version of psp or what fw you are trying to install with desp del cem, just copy it, and put it in the root of the stick you are going to use with timemachine.
here's the link for the tut i found on Timemachine. it is really simple to use.
http://www.consolespot.net/forums/psp-help-tutorials/6263-how-use-tm-v0-1-a.html
also once you have msipl.bin on your normal memstick(the one that you usually use) then you can use the Pandora (jigkick) battery like a normal one. it will launch the normal XMB, or if you hold down the right button (the one that responds to the fw you are trying to launch from TimeMachine then it will launch the emulated XMB.
i'm using 1.50 + 3.40 hybrid fw on my timemachine, and it works really well. also i would suggest for all of those who have a slim to get the sony mega battery pack cover, so that you can hold the pandora(fat) battery in your slim. i did.
im just really excited that i got it working and about Daedalus R14 Beta2, and that i can use the pandora batt with my psp withought anything but the msipl.bin on my memstick. =D
sorry, i see that that link got cut off here it is again, just remove the spaces (if there are any)
http://www.consolespot.net/forums/psp-help-tutorials/
6263-how-use-tm-v0-1-a.html
sorry about that. :)
Another month passes by
StrmnNrmn hasn't updated for so long i bet people are spamming his email address: strmnnrmn@gmail.com
Doubt he checks it thou, he'd obviously have a separate email for Daedalus.
@Swish
Lol you shouldn't have given out his e-mail.. Now he's gona get EVEN MORE spam. I still think he is working on it.. But I can't let the thought out of my mind that there is a chance it's dead...
I bet its gonna be like r9 where there wasnt an update for months, but take a while longer.
This situation is a bit different thou Strmnnrmn didn't even make a comment when his beta got leaked, not that i expected him to :P
Im pretty sure Strmnnrmn is known in the past for just dropping projects just leaving them with no say so if he did im not surprised but hey thats his decision idk why you guys keep whining why do you thin he releases the source code every release so some one can do something with it update find the bugs w.e you gotta do all the time you you waste coming to see if theres an update and asking him for an update you couldve done some thing to update the emulator or learn coding by now, to tell you the truth been here since he opened up the blog and its a great emu but give the guy a break hes not some psycho that sits behind his computer all day long coding a psp emu and hes doin git for free but hey it is what it is and I highly doubt all that shit that hes using different usernames for what? that time he spends using usernames he could just put and update? makes sense? no?
Oh my God!I was going to die because I couldn't breathe! Please, use commas!!!!Or dots!
@ armen
We're not whining we're just talking about it, there's a difference.
You're the one complaining going on and on.
If anyone wants my gamesave for Mario 64 (120 stars), you're welcome to ask for the link. Everyone's probably gotten 120 by now, but ehh...oh well.
You people will never listen, CaptainMorgan4 did not make that build. He has no proof / evidence that he did..
All he did was change the icons...
Blah... It's a wonder we devs get a headache, the fake devs always come out and say OMFG this build the other dev gave me is mine.. This happens all the time with LUA and its killing everyone off.
@armen amen for that comment, we need some more of your type of people.. None of the ignorant type for me anymore. Sick of it.
Now if I have to say this again i'll scream, that beta you talk about isn't really a beta.. Its more or less a SVN build which anyone can do with SVN knowledge, (Ask CaptainMorgan4 about SVN's he thinks he knows shitloads yet cant even grab a source alone) also people require compiler knowledge which is no walk in the park. Daedalus SVN builds sometimes can take more time to compile than people think. Don't get me wrong there, lots of bugs to squash before it would even run.
Get over it you nutters!
Wally
@ Wally
You put a build together didn't you. Was it just bug fixed svn? If so do you mind sharing? I'll help update the SVN and also work on doing as much bug fixing as possible. Either that or put together some sort of separate edition and if Strmnnrmn comes back I'll give him the changes I made and see what he has new and hopefully revive this project from the ashes.
yea hopefully wally can message you. ive been looking forward to this for a long time. let us know if or when wally contacts you just to give us hope back
Nintendo 64 opcodes
Part A: Brief list released on 98-02-19
----------------------------------------------------------------------------
****************************************************************************
** Load and Store Instructions **
****************************************************************************
LB rt,offset(base) Load Byte
LBU rt,offset(base) Load Byte Unsigned
LD rt,offset(base) Load Doubleword
LDL rt,offset(base) Load Doubleword Left
LDR rt,offset(base) Load Doubleword Right
LH rt,offset(base) Load Halfword
LHU rt,offset(base) Load Halfword Unsigned
LL rt,offset(base) Load Linked word
LLD rt,offset(base) Load Linked Doubleword
LW rt,offset(base) Load Word
LWL rt,offset(base) Load Word Left
LWR rt,offset(base) Load Word Right
LWU rt,offset(base) Load Word Unsigned
SB rt,offset(base) Store Byte
SC rt,offset(base) Store Conditional word
SCD rt,offset(base) Store Conditional Doubleword
SD rt,offset(base) Store Doubleword
SDL rt,offset(base) Store Doubleword Left
SDR rt,offset(base) Store Doubleword Right
SH rt,offset(base) Store Halfword
SW rt,offset(base) Store Word
SWL rt,offset(base) Store Word Left
SWR rt,offset(base) Store Word Right
SYNC SYNChronize shared memory
****************************************************************************
** Atithmetic Instructions **
****************************************************************************
ADD rd,rs,rt ADD word
ADDI rt,rs,immediate ADD Immediate word
ADDIU rt,rs,immediate Add Immediate Unsigned word
ADDU rd,rs,rt Add Unsigned word
AND rd,rs,rt AND
ANDI rt,rs,immediate AND Immediate
DADD rd,rs,rt Doubleword ADD
DADDI rt,rs,immediate Doubleword ADD Immediate
DADDIU rt,rs,immediate Doubleword ADD Immediate Unsigned
DADDU rd,rs,rt Doubleword ADD Unsigned
DDIV rs,rt Doubleword DIVide
DDIVU rs,rt Doubleword DIVide Unsigned
DIV rs,rt DIVide word
DIVU rs,rt DIVide Unsigned word
DMULT rs,rt Doubleword MULTiply
DMULTU rs,rt Doubleword MULTiply Unsigned
DSLL rd,rt,sa Doubleword Shift Left Logical
DSLL32 rd,rt,sa Doubleword Shift Left Logical +32
DSLLV rd,rt,rs Doubleword Shift Left Logical Variable
DSRA rd,rt,sa Doubleword Shift Right Arithmetic
DSRA32 rd,rt,sa Doubleword Shift Right Arithmetic +32
DSRAV rd,rt,rs Doubleword Shift Right Arithmetic Variable
DSRL rd,rt,sa Doubleword Shift Right Logical
DSRL32 rd,rt,sa Doubleword Shift Right Logical +32
DSRLV rd,rt,rs Doubleword Shift Right Logical Variable
DSUB rd,rs,rt Doubleword SUBtract
DSUBU rd,rs,rt Doubleword SUBtract Unsigned
LUI rt,immediate Load Upper Immediate
MFHI rd Move From HI register
MFLO rd Move From LO register
MTHI rd Move To HI register
MTLO rd Move To LO register
MULT rs,rt MULTiply word
MULTU rs,rt MULTiply Unsigned word
NOR rd,rs,rt Not OR
OR rd,rs,rt OR
ORI rt,rs,immediate OR Immediate
SLL rd,rt,sa Shift word Left Logical
SLLV rd,rt,rs Shift word Left Logical Variable
SLT rd,rs,rt Set on Less Than
SLTI rt,rs,immediate Set on Less Than Immediate
SLTIU rt,rs,immediate Set on Less Than Immediate Unsigned
SLTU rd,rs,rt Set on Less Than Unsigned
SRA rd,rt,sa Shift word Right Arithmetic
SRAV rd,rt,rs Shift word Right Arithmetic Variable
SRL rd,rt,sa Shift word Right Logical
SRLV rd,rt,rs Shift word Right Logical Variable
SUB rd,rs,rt SUBtract word
SUBU rd,rs,rt SUBtract Unsigned word
XOR rd,rs,rt eXclusive OR
XORI rt,rs,immediate eXclusive OR Immediate
****************************************************************************
** Jump and Branch Instructions **
****************************************************************************
BEQ rs,rt,offset Branch on EQual
BEQL rs,rt,offset Branch on EQual Likely
BGEZ rs,offset Branch on Greater than or Equal to Zero
BGEZAL rs,offset Branch on Greater than or Equal to Zero And Link
BGEZALL rs,offset Branch on Greater than or Equal to Zero And Link Likely
BGEZL rs,offset Branch on Greater than or Equal to Zero Likely
BGTZ rs,offset Branch on Greater than Zero
BGTZL rs,offset Branch on Greater than Zero Likely
BLEZ rs,offset Branch on Less than or Equal to Zero
BLEZL rs,offset Branch on Less than or Equal to Zero Likely
BLTZ rs,offset Branch on Less than Zero
BLTZAL rs,offset Branch on Less than Zero And Link
BLTZALL rs,offset Branch on Less than Zero And Link Likely
BLTZL rs,offset Branch on Less than Zero Likely
BNE rs,rt,offset Branch on Not Equal
BNEL rs,rt,offset Branch on Not Equal Likely
J target Jump
JAL target Jump And Link
JALR rs,rd Jump And Link Register
JR rs Jump Register
****************************************************************************
** Special Instructions **
****************************************************************************
BREAK offset BREAKpoint
SYSCALL offset SYStem CALL
****************************************************************************
** Exception Instructions **
****************************************************************************
TEQ rs,rt Trap if EQual
TEQI rs,immediate Trap if EQual Immediate
TGE rs,rt Trap if Greater Than or Equal
TGEI rs,immediate Trap if Greater Than or Equal Immediate
TGEIU rs,immediate Trap if Greater Than or Equal Immediate Unsigned
TGEU rs,rt Trap if Greater Than or Equal Unsigned
TLT rs,rt Trap if Less Than
TLTI rs,immediate Trap if Less Than Immediate
TLTIU rs,immediate Trap if Less Than Immediate Unsigned
TLTU rs,rt Trap if Less Than Unsigned
TNE rs,rt Trap if not Equal
TNEI rs,immediate Trap if not Equal Immediate
****************************************************************************
** System Control Processor (COP0) Instructions **
****************************************************************************
CACHE op,offset(base) CACHE
DMFC0 rt,fs Doubleword Move From CP0
DMTC0 rt,fs Doubleword Move To CP0
ERET Return from Exception
MFC0 rt,fs Move Word From CP0
MTC0 rt,fs Move Word To CP0
TLBP Probe TLB for Matching Entry
TLBR Read Indexed TLB Entry
TLBWI Write Indexed TLB Entry
TLBWR Write Random TLB Entry
****************************************************************************
** Floating-point Unit (COP1) instructions **
****************************************************************************
ABS.fmt fd,fs floating-point ABSolute value
ADD.fmt fd,fs,ft floating-point ADD
BC1F offset Branch on FP False
BC1FL offset Branch on FP False Likely
BC1T offset Branch on FP True
BC1TL offset Branch on FP True Likely
C.cond.fmt fs,ft floating-point floating point Compare
CEIL.L.fmt fd,fs floating-point CEILing convert to Long fixed-point
CEIL.W.fmt fd,fs floating-point CEILing convert to Word fixed-point
CFC1 rt,fs Move control word From Floating-Point
CTC1 rt,fs Move control word To Floating-Point
CVT.D.fmt fd,fs floating-point ConVerT to Double floating-point
CVT.L.fmt fd,fs floating-point ConVerT to Long fixed-point
CVT.S.fmt fd,fs floating-point ConVerT to Single floating-point
CVT.W.fmt fd,fs floating-point ConVerT to Word fixed-point
DIV.fmt fd,fs,ft floating-point DIVide
DMFC1 rt,fs Doubleword Move From Floating-Point
DMTC1 rt,fs Doubleword Move To Floating-Point
FLOOR.L.fmt fd,fs floating-point FLOOR convert to Long fixed-point
FLOOR.W.fmt fd,fs floating-point FLOOR convert to Word fixed-point
LDC1 rt,offset(base) Load Doubleword to Floating-Point
LWC1 rt,offset(base) Load Word to Floating-Point
MFC1 rt,fs Move Word From Floating-Point
MOV.fmt fd,fs floating-point MOVe
MTC1 rt,fs Move Word To Floating-Point
MUL.fmt fd,fs,ft floating-point MULtiply
NEG.fmt fd,fs floating-point NEGate
ROUND.L.fmt fd,fs floating-point ROUND to Long fixed-point
ROUND.W.fmt fd,fs floating-point ROUND to Word fixed-point
SDC1 rt,offset(base) Store Doubleword from Floating-Point
SQRT.fmt fd,fs floating-point SQuare RooT
SUB.fmt fd,fs,ft floating-point SUBtract
SWC1 rt,offset(base) Store Word from Floating-Point
TRUNC.L.fmt fd,fs floating-point TRUNCate to Long fixed-point
TRUNC.W.fmt fd,fs floating-point TRUNCate to Word fixed-point
Part B: Detailed list released on 98-02-19
----------------------------------------------------------------------------
I need information/answers about the following:
* Info about COP1 registers.
* Information about COP2!!! instructions, anything!!
* How do i correctly decode address of 26-bit Jump instructions (J, JAL) ?
* How do i correctly decode address of 16-bit Branch instructions?
----------------------------------------------------------------------------
COP0 registers:
---------------
00h = Index 08h = BadVAddr 10h = Config 18h = *RESERVED*
01h = Random 09h = Count 11h = LLAddr 19h = *RESERVED*
02h = EntryLo0 0Ah = EntryHi 12h = WatchLo 1Ah = PErr
03h = EntryLo1 0Bh = Compare 13h = WatchHi 1Bh = CacheErr
04h = Context 0Ch = Status 14h = XContext 1Ch = TagLo
05h = PageMask 0Dh = Cause 15h = *RESERVED* 1Dh = TagHi
06h = Wired 0Eh = EPC 16h = *RESERVED* 1Eh = ErrorEPC
07h = *RESERVED* 0Fh = PRevID 17h = *RESERVED* 1Fh = *RESERVED*
Main CPU registers:
-------------------
00h = r0/reg0 08h = t0/reg8 10h = s0/reg16 18h = t8/reg24
01h = at/reg1 09h = t1/reg9 11h = s1/reg17 19h = t9/reg25
02h = v0/reg2 0Ah = t2/reg10 12h = s2/reg18 1Ah = k0/reg26
03h = v1/reg3 0Bh = t3/reg11 13h = s3/reg19 1Bh = k1/reg27
04h = a0/reg4 0Ch = t4/reg12 14h = s4/reg20 1Ch = gp/reg28
05h = a1/reg5 0Dh = t5/reg13 15h = s5/reg21 1Dh = sp/reg29
06h = a2/reg6 0Eh = t6/reg14 16h = s6/reg22 1Eh = s8/reg30
07h = a3/reg7 0Fh = t7/reg15 17h = s7/reg23 1Fh = ra/reg31
****************************************************************************
** Load and Store Instructions **
****************************************************************************
-----------------------------------------------------------------
| LB | Load Byte |
|-----------|---------------------------------------------------|
|100000 (32)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LBU rt, offset(base)
Purpose: To load a byte from memory as a signed value.
Descrip: rt = byte[base+offset]
-----------------------------------------------------------------
| LBU | Load Byte Unsigned |
|-----------|---------------------------------------------------|
|100100 (36)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LBU rt, offset(base)
Purpose: To load a byte from memory as an unsigned value.
Descrip: rt = byte[base+offset]
-----------------------------------------------------------------
| LD | Load Doubleword |
|-----------|---------------------------------------------------|
|110111 (55)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LD rt, offset(base)
Purpose: To load a doubleword from memory.
Descrip: rt = doubleword[base+offset]
-----------------------------------------------------------------
| LDL | Load Doubleword Left |
|-----------|---------------------------------------------------|
|011010 (26)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LDL rt, offset(base)
Purpose: To load the most-significant part of a doubleword from
an unaligned memory address.
Descrip: left(rt) = right[base+offset]
-----------------------------------------------------------------
| LDR | Load Doubleword Right |
|-----------|---------------------------------------------------|
|011011 (27)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LDR rt, offset(base)
Purpose: To load the least-significant part of a doubleword from
an unaligned memory address.
Descrip: right(rt) = left[base+offset]
-----------------------------------------------------------------
| LH | Load Halfword |
|-----------|---------------------------------------------------|
|100001 (33)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LH rt, offset(base)
Purpose: To load a halfword from memory as a signed value.
Descrip: rt = halfword[base+offset]
-----------------------------------------------------------------
| LHU | Load Halfword Unsigned |
|-----------|---------------------------------------------------|
|100101 (37)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LHU rt, offset(base)
Purpose: To load a halfword from memory as an unsigned value.
Descrip: rt = halfword[base+offset]
-----------------------------------------------------------------
| LL | Load Linked Word |
|-----------|---------------------------------------------------|
|110000 (48)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LL rt, offset(base)
Purpose: To load a word from memory for an atomic read-modify-write.
-----------------------------------------------------------------
| LLD | Load Linked Doubleword |
|-----------|---------------------------------------------------|
|110100 (52)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LLD rt, offset(base)
Purpose: To load a doubleword from memory for an atomic read-modify-write.
-----------------------------------------------------------------
| LW | Load Word |
|-----------|---------------------------------------------------|
|100011 (35)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LW rt, offset(base)
Purpose: To load a word from memory as a signed value.
Descrip: rt = word[base+offset]
-----------------------------------------------------------------
| LWL | Load Word Left |
|-----------|---------------------------------------------------|
|100010 (34)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LWL rt, offset(base)
Purpose: To load the most-significant part of a word as a
signed value from an unaligned memory address.
Descrip: left(rt) = right[base+offset]
-----------------------------------------------------------------
| LWR | Load Word Right |
|-----------|---------------------------------------------------|
|100110 (38)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LWR rt, offset(base)
Purpose: To load the least-significant part of a word from an
unaligned memory address as a signed value.
Descrip: right(rt) = left[base+offset]
-----------------------------------------------------------------
| LWU | Load Word Unsigned |
|-----------|---------------------------------------------------|
|100111 (39)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LWU rt, offset(base)
Purpose: To load a word from memory as an unsigned value.
Descrip: rt = word[base+offset]
-----------------------------------------------------------------
| SB | Store Byte |
|-----------|---------------------------------------------------|
|101000 (40)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SB rt, offset(base)
Purpose: To store a byte to memory.
Descrip: byte[base+offset] = rt
-----------------------------------------------------------------
| SC | Store Conditional Word |
|-----------|---------------------------------------------------|
|111000 (56)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SC rt, offset(base)
Purpose: To store a word to memory to complete an atomic read-modify-write.
-----------------------------------------------------------------
| SCD | Store Conditional Doubleword |
|-----------|---------------------------------------------------|
|111100 (60)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SCD rt, offset(base)
Purpose: To store a doubleword to memory to complete an atomic
read-modify-write.
-----------------------------------------------------------------
| SD | Store Doubleword |
|-----------|---------------------------------------------------|
|111111 (63)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SD rt, offset(base)
Purpose: To store a doubleword to memory.
Descrip: doulbeword[base+offset] = rt
-----------------------------------------------------------------
| SDL | Store Doubleword Left |
|-----------|---------------------------------------------------|
|101100 (44)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SDL rt, offset(base)
Purpose: To store the most-significant part of a doubleword to
an unaligned memory address.
Descrip: right[base+offset] = left(rt)
-----------------------------------------------------------------
| SDR | Store Doubleword Right |
|-----------|---------------------------------------------------|
|101101 (45)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SDR rt, offset(base)
Purpose: To store the least-significant part of a doubleword to
an unaligned memory address.
Descrip: left[base+offset] = right(rt)
-----------------------------------------------------------------
| SH | Store Halfword |
|-----------|---------------------------------------------------|
|101001 (41)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SH rt, offset(base)
Purpose: To store a halfword to memory.
Descrip: halfword[base+offset] = rt
-----------------------------------------------------------------
| SW | Store Word |
|-----------|---------------------------------------------------|
|101011 (43)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SW rt, offset(base)
Purpose: To store a word to memory.
Descrip: word[base+offset] = rt
-----------------------------------------------------------------
| SWL | Store Word Left |
|-----------|---------------------------------------------------|
|101010 (42)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SWL rt, offset(base)
Purpose: To store the most-significant part of a word to an
unaligned memory address.
Descrip: right[base+offset] = left(rt)
-----------------------------------------------------------------
| SWR | Store Word Right |
|-----------|---------------------------------------------------|
|101110 (46)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SWR rt, offset(base)
Purpose: To store the least-significant part of a word to an
unaligned memory address.
Descrip: left[base+offset] = right(rt)
-----------------------------------------------------------------
| SYNC | SYNChronize shared memory |
|-----------|---------------------------------------------------|
| 000000 | 0000 0000 0000 000 | stype |001111 (15)|
------6-------------------15-------------------5---------6-------
Format: SYNC (stype = 0 implied)
Purpose: To order loads and stores to shared memory in a
multiprocessor system.
****************************************************************************
** Atithmetic Instructions **
****************************************************************************
-----------------------------------------------------------------
| ADD | ADD word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100000 (32)|
------6----------5---------5---------5---------5----------6------
Format: ADD rd, rs, rt
Purpose: To add 32-bit integers. If overflow occurs, then trap.
Descrip: rd = rs + rt
-----------------------------------------------------------------
| ADDI | ADD Immediate word |
|-----------|---------------------------------------------------|
|001000 (8) | rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: ADDI rt, rs, immediate
Purpose: To add a constant to a 32-bit integer.
If overflow occurs, then trap.
Descrip: rt = rs + immediate
-----------------------------------------------------------------
| ADDIU | ADD Immediate Unsigned word |
|-----------|---------------------------------------------------|
|001001 (9) | rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: ADDIU rt, rs, immediate
Purpose: To add a constant to a 32-bit integer.
Descrip: rt = rs + immediate
-----------------------------------------------------------------
| ADDU | ADD Unsigned word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100001 (33)|
------6----------5---------5---------5---------5----------6------
Format: ADDU rd, rs, rt
Purpose: To add 32-bit integers.
Descrip: rd = rs + rt
-----------------------------------------------------------------
| AND | AND |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100100 (36)|
------6----------5---------5---------5---------5----------6------
Format: AND rd, rs, rt
Purpose: To do a bitwise logical AND.
Descrip: rd = (rs AND rt)
-----------------------------------------------------------------
| ANDI | AND Immediate |
|-----------|---------------------------------------------------|
|001100 (12)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: ANDI rt, rs, immediate
Purpose: To do a bitwise logical AND with a constant.
Descrip: rd = (rs AND immediate)
-----------------------------------------------------------------
| DADD | Doubleword ADD |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101100 (44)|
------6----------5---------5---------5---------5----------6------
Format: DADD rd, rs, rt
Purpose: To add 64-bit integers. If overflow occurs, then trap.
Descrip: rd = rs + rt
-----------------------------------------------------------------
| DADDI | Doubleword ADD Immediate |
|-----------|---------------------------------------------------|
|011000 (24)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: DADDI rt, rs, immediate
Purpose: To add a constant to a 64-bit integer.
If overflow occurs, then trap.
Descrip: rt = rs + immediate
-----------------------------------------------------------------
| DADDIU | Doubleword ADD Immediate Unsigned |
|-----------|---------------------------------------------------|
|011001 (25)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: DADDIU rt, rs, immediate
Purpose: To add a constant to a 64-bit integer.
Descrip: rt = rs + immediate
-----------------------------------------------------------------
| DADDU | Doubleword ADD Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101101 (45)|
------6----------5---------5---------5---------5----------6------
Format: DADDU rd, rs, rt
Purpose: To add 64-bit integers.
Descrip: rd = rs + rt
-----------------------------------------------------------------
| DDIV | Doubleword DIVide |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011110 (30)|
------6----------5---------5--------------10--------------6------
Format: DDIV rs, rt
Purpose: To divide 64-bit signed integers.
Descrip: LO = rs / rt; HI = rs MOD rt
-----------------------------------------------------------------
| DDIVU | Doubleword DIVide Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011111 (31)|
------6----------5---------5--------------10--------------6------
Format: DDIVU rs, rt
Purpose: To divide 64-bit unsigned integers.
Descrip: LO = rs / rt; HI = rs MOD rt
-----------------------------------------------------------------
| DIV | DIVide word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011010 (26)|
------6----------5---------5--------------10--------------6------
Format: DIV rs, rt
Purpose: To divide 32-bit signed integers.
Descrip: LO = rs / rt; HI = rs MOD rt
-----------------------------------------------------------------
| DIVU | DIVide Unsigned word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011011 (27)|
------6----------5---------5--------------10--------------6------
Format: DIVU rs, rt
Purpose: To divide 32-bit unsigned integers.
Descrip: LO = rs / rt; HI = rs MOD rt
-----------------------------------------------------------------
| DMULT | Doubleword MULTiply |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011100 (28)|
------6----------5---------5--------------10--------------6------
Format: DMULT rs, rt
Purpose: To multiply 64-bit signed integers.
Descrip: LO = low(rs*rt); HI = high(rs*rt)
-----------------------------------------------------------------
| DMULTU | Doubleword MULTiply Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011101 (28)|
------6----------5---------5--------------10--------------6------
Format: DMULTU rs, rt
Purpose: To multiply 64-bit unsigned integers.
Descrip: LO = low(rs*rt); HI = high(rs*rt)
-----------------------------------------------------------------
| DSLL | Doubleword Shift Left Logical |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111000 (56)|
------6----------5---------5---------5---------5----------6------
Format: DSLL rd, rt, sa
Purpose: To left shift a doubleword by a fixed amount -- 0 to 31 bits.
Descrip: rd = rt << sa
-----------------------------------------------------------------
| DSLL32 | Doubleword Shift Left Logical +32 |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111100 (60)|
------6----------5---------5---------5---------5----------6------
Format: DSLL32 rd, rt, sa
Purpose: To left shift a doubleword by a fixed amount -- 32 to 63 bits.
Descrip: rd = rt << (sa+32)
-----------------------------------------------------------------
| DSLLV | Doubleword Shift Left Logical Variable |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |010100 (20)|
------6----------5---------5---------5---------5----------6------
Format: DSLLV rd, rt, rs
Purpose: To left shift a doubleword by a variable number of bits.
Descrip: rd = rt << rs
-----------------------------------------------------------------
| DSRA | Doubleword Shift Right Arithmetic |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111011 (59)|
------6----------5---------5---------5---------5----------6------
Format: DSRA rd, rt, sa
Purpose: To arithmetic right shift a doubleword by a fixed
amount -- 0 to 31 bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| DSRA32 | Doubleword Shift Right Arithmetic +32 |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111111 (63)|
------6----------5---------5---------5---------5----------6------
Format: DSRA32 rd, rt, sa
Purpose: To arithmetic right shift a doubleword by a fixed
amount -- 32-63 bits.
Descrip: rd = rt >> (sa+32)
-----------------------------------------------------------------
| DSRAV | Doubleword Shift Right Arithmetic Variable |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |010111 (23)|
------6----------5---------5---------5---------5----------6------
Format: DSRAV rd, rt, rs
Purpose: To arithmetic right shift a doubleword by a variable
number of bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| DSRL | Doubleword Shift Right Logical |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111010 (58)|
------6----------5---------5---------5---------5----------6------
Format: DSRL rd, rt, sa
Purpose: To logical right shift a doubleword by a fixed amount
-- 0 to 31 bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| DSRL32 | Doubleword Shift Right Logical +32 |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111110 (62)|
------6----------5---------5---------5---------5----------6------
Format: DSRL32 rd, rt, sa
Purpose: To logical right shift a doubleword by a fixed amount
-- 32 to 63 bits.
Descrip: rd = rt >> (sa+32)
-----------------------------------------------------------------
| DSRLV | Doubleword Shift Right Logical Variable |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |010110 (22)|
------6----------5---------5---------5---------5----------6------
Format: DSRLV rd, rt, rs
Purpose: To logical right shift a doubleword by a variable number of bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| DSUB | Doubleword SUBtract |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101110 (46)|
------6----------5---------5---------5---------5----------6------
Format: DSUB rd, rs, rt
Purpose: To subtract 64-bit integers; trap if overflow.
Descrip: rd = rs - rt
-----------------------------------------------------------------
| DSUBU | Doubleword SUBtract Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101111 (47)|
------6----------5---------5---------5---------5----------6------
Format: DSUBU rd, rs, rt
Purpose: To subtract 64-bit integers.
Descrip: rd = rs - rt
-----------------------------------------------------------------
| LUI | Load Upper Immediate |
|-----------|---------------------------------------------------|
|001111 (15)| 00000 | rt | immediate |
------6----------5---------5-------------------16----------------
Format: LUI rt, immediate
Purpose: To load a constant into the upper half of a word.
Descrip: rt = immediate * 10000h
-----------------------------------------------------------------
| MFHI | Move From HI register |
|-----------|---------------------------------------------------|
| 000000 | 0000 0000 00 | rd | 00000 |010000 (16)|
------6---------------10-------------5---------5----------6------
Format: MFHI rd
Purpose: To copy the special purpose HI register to a GPR.
Descrip: rd = HI
-----------------------------------------------------------------
| MFLO | Move From LO register |
|-----------|---------------------------------------------------|
| 000000 | 0000 0000 00 | rd | 00000 |010010 (18)|
------6---------------10-------------5---------5----------6------
Format: MFLO rd
Purpose: To copy the special purpose LO register to a GPR.
Descrip: rd = LO
-----------------------------------------------------------------
| MTHI | Move To HI register |
|-----------|---------------------------------------------------|
| 000000 | rs | 0000 0000 0000 000 |010001 (17)|
------6----------5------------------15--------------------6------
Format: MTHI rs
Purpose: To copy a GPR to the special purpose HI register.
-----------------------------------------------------------------
| MTLO | Move To LO register |
|-----------|---------------------------------------------------|
| 000000 | rs | 0000 0000 0000 000 |010011 (19)|
------6----------5------------------15--------------------6------
Format: MTLO rs
Purpose: To copy a GPR to the special purpose LO register.
-----------------------------------------------------------------
| MULT | MULTiply word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011000 (24)|
------6----------5---------5--------------10--------------6------
Format: MULT rs, rt
Purpose: To multiply 32-bit signed integers.
Descrip: LO = low(rs*rt); HI = high(rs*rt)
-----------------------------------------------------------------
| MULTU | MULTiply Unsigned word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011001 (25)|
------6----------5---------5--------------10--------------6------
Format: MULTU rs, rt
Purpose: To multiply 32-bit unsigned integers.
Descrip: LO = low(rs*rt); HI = high(rs*rt)
-----------------------------------------------------------------
| NOR | Not OR |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100111 (39)|
------6----------5---------5---------5---------5----------6------
Format: NOR rd, rs, rt
Purpose: To do a bitwise logical NOT OR.
Descrip: rd = (rs NOR rt)
-----------------------------------------------------------------
| OR | OR |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100101 (37)|
------6----------5---------5---------5---------5----------6------
Format: OR rd, rs, rt
Purpose: To do a bitwise logical OR.
Descrip: rd = (rs OR rt)
-----------------------------------------------------------------
| ORI | OR Immediate |
|-----------|---------------------------------------------------|
|001101 (13)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: ORI rt, rs, immediate
Purpose: To do a bitwise logical OR with a constant.
Descrip: rt = (rs NOR immediate)
-----------------------------------------------------------------
| SLL | Shift word Left Logical |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |000000 (0) |
------6----------5---------5---------5---------5----------6------
Format: SLL rd, rt, sa
Purpose: To left shift a word by a fixed number of bits.
Comment: SLL r0, r0, r0 is equal to a NOP (No OPeration)
Descrip: rd = rt << sa
-----------------------------------------------------------------
| SLLV | Shift word Left Logical Variable |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |000100 (4) |
------6----------5---------5---------5---------5----------6------
Format: SLLV rd, rt, rs
Purpose: To left shift a word by a variable number of bits.
Descrip: rd = rt << sa
-----------------------------------------------------------------
| SLT | Set on Less Than |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101010 (42)|
------6----------5---------5---------5---------5----------6------
Format: SLT rd, rs, rt
Purpose: To record the result of a less-than comparison.
Descrip: if rs < rt then rd = 1 else rd = 0
-----------------------------------------------------------------
| SLTI | Set on Less Than Immediate |
|-----------|---------------------------------------------------|
|001010 (10)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: SLTI rt, rs, immediate
Purpose: To record the result of a less-than comparison with a constant.
Descrip: if rs < immediate then rd = 1 else rd = 0
-----------------------------------------------------------------
| SLTIU | Set on Less Than Immediate Unsigned |
|-----------|---------------------------------------------------|
|001011 (11)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: SLTIU rt, rs, immediate
Purpose: To record the result of an unsigned less-than
comparison with a constant.
Descrip: if rs < immediate then rd = 1 else rd = 0
-----------------------------------------------------------------
| SLTU | Set on Less Than Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101011 (43)|
------6----------5---------5---------5---------5----------6------
Format: SLTU rd, rs, rt
Purpose: To record the result of an unsigned less-than comparison.
Descrip: if rs < rt then rd = 1 else rd = 0
-----------------------------------------------------------------
| SRA | Shift word Right Arithmetic |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |000011 (3) |
------6----------5---------5---------5---------5----------6------
Format: SRA rd, rt, sa
Purpose: To arithmetic right shift a word by a fixed number of bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| SRAV | Shift word Right Arithmetic Variable |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |000111 (7) |
------6----------5---------5---------5---------5----------6------
Format: SRAV rd, rt, rs
Purpose: To arithmetic right shift a word by a variable number of bits.
Descrip: rd = rt >> rs
-----------------------------------------------------------------
| SRL | Shift word Right Logical |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |000010 (2) |
------6----------5---------5---------5---------5----------6------
Format: SRL rd, rt, sa
Purpose: To logical right shift a word by a fixed number of bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| SRLV | Shift word Right Logical Variable |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |000110 (6) |
------6----------5---------5---------5---------5----------6------
Format: SRLV rd, rt, rs
Purpose: To logical right shift a word by a variable number of bits.
Descrip: rd = rt >> rs
-----------------------------------------------------------------
| SUB | SUBtract word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100010 (34)|
------6----------5---------5---------5---------5----------6------
Format: SUB rd, rs, rt
Purpose: To subtract 32-bit integers. If overflow occurs, then trap.
Descrip: rd = rs - rt
-----------------------------------------------------------------
| SUBU | SUBtract Unsigned word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100011 (35)|
------6----------5---------5---------5---------5----------6------
Format: SUBU rd, rs, rt
Purpose: To subtract 32-bit integers. No trap on overflow.
Descrip: rd = rs - rt
-----------------------------------------------------------------
| XOR | eXclusive OR |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100110 (38)|
------6----------5---------5---------5---------5----------6------
Format: XOR rd, rs, rt
Purpose: To do a bitwise logical EXCLUSIVE OR.
Descrip: rd = (rs XOR rt)
-----------------------------------------------------------------
| XORI | eXclusive OR Immediate |
|-----------|---------------------------------------------------|
|001110 (14)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: XORI rt, rs, immediate
Purpose: To do a bitwise logical EXCLUSIVE OR with a constant.
Descrip: rd = (rs XOR immediate)
****************************************************************************
** Jump and Branch Instructions **
****************************************************************************
-----------------------------------------------------------------
| BEQ | Branch on EQual |
|-----------|---------------------------------------------------|
|000100 (4) | rs | rt | offset |
------6----------5---------5-------------------16----------------
Format: BEQ rs, rt, offset
Purpose: To compare GPRs then do a PC-relative conditional branch.
Descrip: branch if rs = rt
-----------------------------------------------------------------
| BEQL | Branch on EQual Likley |
|-----------|---------------------------------------------------|
|010100 (20)| rs | rt | offset |
------6----------5---------5-------------------16----------------
Format: BEQL rs, rt, offset
Purpose: To compare GPRs then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs = rt
-----------------------------------------------------------------
| BGEZ | Branch on Greater than or Equal to Zero |
|-----------|---------------------------------------------------|
| 000001 | rs |00001 (1)| offset |
------6----------5---------5-------------------16----------------
Format: BGEZ rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch.
Descrip: branch if rs >= 0 (signed)
-----------------------------------------------------------------
| BGEZAL | Branch on Greater than or Equal to Zero And Link |
|-----------|---------------------------------------------------|
| 000001 | rs |10001(17)| offset |
------6----------5---------5-------------------16----------------
Format: BGEZAL rs, offset
Purpose: To test a GPR then do a PC-relative conditional procedure call.
Descrip: branch if rs >= 0 (signed) (return address in ra)
-----------------------------------------------------------------
| BGEZALL | Branch on Greater than or Equal to Zero And Link Likley
|-----------|---------------------------------------------------|
| 000001 | rs |10011(19)| offset |
------6----------5---------5-------------------16----------------
Format: BGEZALL rs, offset
Purpose: To test a GPR then do a PC-relative conditional procedure call;
execute the delay slot only if the branch is taken.
Descrip: branch if rs >= 0 (signed) (return address in ra)
-----------------------------------------------------------------
| BGEZL | Branch on Greater than or Equal to Zero Likley |
|-----------|---------------------------------------------------|
| 000001 | rs |00011 (3)| offset |
------6----------5---------5-------------------16----------------
Format: BGEZL rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs >= 0 (signed)
-----------------------------------------------------------------
| BGTZ | Branch on Greater than Zero |
|-----------|---------------------------------------------------|
|000111 (7) | rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BGTZ rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch.
Descrip: branch if rs > 0 (signed)
-----------------------------------------------------------------
| BGTZL | Branch on Greater Than Zero Likley |
|-----------|---------------------------------------------------|
|010111 (23)| rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BGTZL rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs > 0 (signed)
-----------------------------------------------------------------
| BLEZ | Branch on Less than or Equal to Zero |
|-----------|---------------------------------------------------|
|000110 (6) | rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BLEZ rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch.
Descrip: branch if rs <= 0 (signed)
-----------------------------------------------------------------
| BLEZL | Branch on Less than or Equal to Zero Likley |
|-----------|---------------------------------------------------|
|010110 (22)| rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BLEZL rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs <= 0 (signed)
-----------------------------------------------------------------
| BLTZ | Branch on Less Than Zero |
|-----------|---------------------------------------------------|
| 000001 | rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BLTZ rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch.
Descrip: branch if rs < 0 (signed)
-----------------------------------------------------------------
| BLTZAL | Branch on Less Than Zero And Link |
|-----------|---------------------------------------------------|
| 000001 | rs | 10000 | offset |
------6----------5---------5-------------------16----------------
Format: BLTZAL rs, offset
Purpose: To test a GPR then do a PC-relative conditional procedure call.
Descrip: branch if rs < 0 (signed) (return address in ra)
-----------------------------------------------------------------
| BLTZALL | Branch on Less Than Zero And Link Likley |
|-----------|---------------------------------------------------|
| 000001 | rs | 10010 | offset |
------6----------5---------5-------------------16----------------
Format: BLTZALL rs, offset
Purpose: To test a GPR then do a PC-relative conditional procedure
call; execute the delay slot only if the branch is taken.
Descrip: branch if rs < 0 (signed) (return address in ra)
-----------------------------------------------------------------
| BLTZL | Branch on Less Than Zero Likley |
|-----------|---------------------------------------------------|
| 000001 | rs |00010 (2)| offset |
------6----------5---------5-------------------16----------------
Format: BLTZL rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs < 0 (signed)
-----------------------------------------------------------------
| BNE | Branch on Not Equal |
|-----------|---------------------------------------------------|
|000101 (5) | rs | rt | offset |
------6----------5---------5-------------------16----------------
Format: BNE rs, rt, offset
Purpose: To compare GPRs then do a PC-relative conditional branch.
Descrip: branch if rs <> rt
-----------------------------------------------------------------
| BNEL | Branch on Not Equal Likley |
|-----------|---------------------------------------------------|
|010101 (21)| rs | rt | offset |
------6----------5---------5-------------------16----------------
Format: BNEL rs, rt, offset
Purpose: To compare GPRs then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs <> rt
-----------------------------------------------------------------
| J | Jump |
|-----------|---------------------------------------------------|
|000010 (2) | instr_index |
------6-------------------------------26-------------------------
Format: J target
Purpose: To branch within the current 256 MB aligned region.
-----------------------------------------------------------------
| JAL | Jump And Link |
|-----------|---------------------------------------------------|
|000011 (3) | instr_index |
------6-------------------------------26-------------------------
Format: JAL target
Purpose: To procedure call within the current 256 MB aligned region.
Descrip: return address in ra
-----------------------------------------------------------------
| JALR | Jump And Link Register |
|-----------|---------------------------------------------------|
| 000000 | rs | 00000 | rd | 00000 |001001 (9) |
------6----------5---------5---------5---------5----------6------
Format: JALR rs, rd
Purpose: To procedure call to an instruction address in a register.
Descrip: return address in rd
-----------------------------------------------------------------
| JR | Jump Register |
|-----------|---------------------------------------------------|
| 000000 | rs | 0000 0000 0000 000 |001000 (8) |
------6----------5------------------15--------------------6------
Format: JR rs
Purpose: To branch to an instruction address in a register.
****************************************************************************
** Special instructions **
****************************************************************************
-----------------------------------------------------------------
| BREAK | BREAKpoint |
|-----------|---------------------------------------------------|
| 000000 | code |001101 (13)|
------6--------------------------20-----------------------6------
Format: BREAK offset
Purpose: To cause a Breakpoint exception.
-----------------------------------------------------------------
| SYSCALL | SYStem CALL |
|-----------|---------------------------------------------------|
| 000000 | code |001100 (12)|
------6--------------------------20-----------------------6------
Format: SYSCALL offset
Purpose: To cause a System Call exception.
****************************************************************************
** Exception Instructions **
****************************************************************************
-----------------------------------------------------------------
| TEQ | Trap if EQual |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110100 (52)|
------6----------5---------5--------------10--------------6------
Format: TEQ rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs = rt then trap
-----------------------------------------------------------------
| TEQI | Trap if EQual Immediate |
|-----------|---------------------------------------------------|
| 000001 | rs |01100(12)| immediate |
------6----------5---------5-------------------16----------------
Format: TEQI rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs = immediate then trap
-----------------------------------------------------------------
| TGE | Trap if Greater or Equal |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110000 (48)|
------6----------5---------5--------------10--------------6------
Format: TGE rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs >= rt then trap
-----------------------------------------------------------------
| TGEI | Trap if Greater or Equal Immediate |
|-----------|---------------------------------------------------|
| 000001 | rs |01000 (8)| immediate |
------6----------5---------5-------------------16----------------
Format: TGEI rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs >= immediate then trap
-----------------------------------------------------------------
| TGEIU | Trap if Greater or Equal Immediate Unsigned |
|-----------|---------------------------------------------------|
| 000001 | rs |01001 (9)| immediate |
------6----------5---------5-------------------16----------------
Format: TGEIU rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs >= immediate then trap
-----------------------------------------------------------------
| TGEU | Trap if Greater or Equal Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110001 (49)|
------6----------5---------5--------------10--------------6------
Format: TGEU rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs >= rt then trap
-----------------------------------------------------------------
| TLT | Trap if Less Than |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110010 (50)|
------6----------5---------5--------------10--------------6------
Format: TLT rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs < rt then trap
-----------------------------------------------------------------
| TLTI | Trap if Less Than Immediate |
|-----------|---------------------------------------------------|
| 000001 | rs |01010(10)| immediate |
------6----------5---------5-------------------16----------------
Format: TLTI rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs < immediate then trap (signed)
-----------------------------------------------------------------
| TLTIU | Trap if Less Than Immediate Unsigned |
|-----------|---------------------------------------------------|
| 000001 | rs |01011(11)| immediate |
------6----------5---------5-------------------16----------------
Format: TLTIU rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs < immediate then trap
-----------------------------------------------------------------
| TLTU | Trap if Less Than Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110011 (51)|
------6----------5---------5--------------10--------------6------
Format: TLTU rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs < rt then trap
-----------------------------------------------------------------
| TNE | Trap if Not Equal |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110110 (54)|
------6----------5---------5--------------10--------------6------
Format: TNE rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs <> rt then trap
-----------------------------------------------------------------
| TNEI | Trap if Not Equal Immediate |
|-----------|---------------------------------------------------|
| 000001 | rs |01110(14)| immediate |
------6----------5---------5-------------------16----------------
Format: TNEI rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs <> immediate then trap
****************************************************************************
** System Control Processor (COP0) Instructions **
****************************************************************************
-----------------------------------------------------------------
| CACHE | CACHE |
|-----------|---------------------------------------------------|
|101111 (47)| base | op | offset |
------6----------5---------5-------------------16----------------
Format: CACHE op, offset(base)
Purpose: The 16-bit offset is sign-extended and added to the contents of
general register base to form a virtual address. The virtual
address is translated to a physical address using the TLB, and the
5-bit sub-opcode specifies a cache operation for that address.
-----------------------------------------------------------------
| DMFC0 | Doubleword Move From CP0 |
|-----------|---------------------------------------------------|
| 010000 |00001 (1)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: DMFC0 rt, rd
Purpose: To copy a doubleword from an FPR to a GPR.
-----------------------------------------------------------------
| DMTC0 | Doubleword Move To CP0 |
|-----------|---------------------------------------------------|
| 010000 |00101 (5)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: DMTC0 rt, rd
Purpose: To copy a doubleword from a GPR to an FPR.
-----------------------------------------------------------------
| ERET | Return from Exception |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 |011000 (24)|
------6------1-------------------19-----------------------6------
Format: ERET
Purpose: ERET is the R4300 instruction for returning from an interrupt,
exception, or error trap. Unlike a branch or jump instruction,
ERET does not execute the next instruction.
-----------------------------------------------------------------
| MFC0 | Move word From CP0 |
|-----------|---------------------------------------------------|
| 010000 |00000 (0)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: MFC0 rt, rd
Purpose: To copy a word from an FPU (CP1) general register to a GPR.
Descrip: rt = COP rd
-----------------------------------------------------------------
| MTC0 | Move word to CP0 |
|-----------|---------------------------------------------------|
| 010000 |00100 (4)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: MTC0 rt, rd
Purpose: To copy a word from a GPR to an FPU (CP1) general register.
Descrip: COP rd = rt
-----------------------------------------------------------------
| TLBP | Translation Lookaside Buffer Probe |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 | 001000 (8)|
------6------1-------------------19-----------------------6------
Format: TLBP
Purpose: The Index register is loaded with the address of the TLB entry
whose contents match the contents of the EntryHi register. If no
TLB entry matches, the high-order bit of the Index register is set.
The architecture does not specify the operation of memory references
associated with the instruction immediately after a TLBP instruction,
nor is the operation specified if more than one TLB entry matches.
-----------------------------------------------------------------
| TLBR | Translation Lookaside Buffer Read |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 | 000001 (1)|
------6------1-------------------19-----------------------6------
Format: TLBR
Purpose: The G bit (which controls ASID matching) read from the TLB is
written into both of the EntryLo0 and EntryLo1 registers.
The EntryHi and EntryLo registers are loaded with the contents of
the TLB entry pointed at by the contents of the TLB Index register.
The operation is invalid (and the results are unspecified) if the
contents of the TLB Index register are greater than the number of
TLB entries in the processor.
-----------------------------------------------------------------
| TLBWI | Translation Lookaside Buffer Write Index |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 | 000010 (2)|
------6------1-------------------19-----------------------6------
Format: TLBWI
Purpose: The G bit of the TLB is written with the logical AND of the G bits
in the EntryLo0 and EntryLo1 registers. The TLB entry pointed at by
the contents of the TLB Index register is loaded with the contents
of the EntryHi and EntryLo registers. The operation is invalid (and
the results are unspecified) if the contents of the TLB Index
register are greater than the number of TLB entries in the processor.
-----------------------------------------------------------------
| TLBWR | Translation Lookaside Buffer Write Random |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 | 000110 (6)|
------6------1-------------------19-----------------------6------
Format: TLBWR
Purpose: The G bit of the TLB is written with the logical AND of the G bits
in the EntryLo0 and EntryLo1 registers. The TLB entry pointed at by
the contents of the TLB Random register is loaded with the contents
of the EntryHi and EntryLo registers.
****************************************************************************
** Floating-point Unit (COP1) instructions **
****************************************************************************
fmt = 10000b (.S, Single) fmt = 10001b (.D, Double)
fmt = 10100b (.W, Word) fmt = 10101b (.L, Long)
-----------------------------------------------------------------
| ABS.fmt | floating-point ABSolute value |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 000101 (5)|
------6----------5---------5---------5---------5----------6------
Format: ABS.S fd, fs
ABS.D fd, fs
Purpose: To compute the absolute value of an FP value.
-----------------------------------------------------------------
| ADD.fmt | floating-point ADD |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | fd | 000000 (0)|
------6----------5---------5---------5---------5----------6------
Format: ADD.S fd, fs, ft
ADD.D fd, fs, ft
Purpose: To add FP values.
-----------------------------------------------------------------
| BC1F | Branch on FP False |
|-----------|---------------------------------------------------|
| 010001 |01000 (8)| cc |nd|tf| offset |
| | | | 0| 0| |
------6----------5-------3---1--1--------------16----------------
Format: BC1F offset (cc = 0 implied)
BC1F cc, offset
Purpose: To test an FP condition code and do a PC-relative
conditional branch.
-----------------------------------------------------------------
| BC1FL | Branch on FP False Likley |
|-----------|---------------------------------------------------|
| 010001 |01000 (8)| cc |nd|tf| offset |
| | | | 1| 0| |
------6----------5-------3---1--1--------------16----------------
Format: BC1FL offset (cc = 0 implied)
BC1FL cc, offset
Purpose: To test an FP condition code and do a PC-relative conditional
branch; execute the delay slot only if the branch is taken.
-----------------------------------------------------------------
| BC1T | Branch on FP True |
|-----------|---------------------------------------------------|
| 010001 |01000 (8)| cc |nd|tf| offset |
| | | | 0| 1| |
------6----------5-------3---1--1--------------16----------------
Format: BC1T offset (cc = 0 implied)
BC1T cc, offset
Purpose: To test an FP condition code and do a PC-relative
conditional branch.
-----------------------------------------------------------------
| BC1TL | Branch on FP True Likley |
|-----------|---------------------------------------------------|
| 010001 |01000 (8)| cc |nd|tf| offset |
| | | | 1| 1| |
------6----------5-------3---1--1--------------16----------------
Format: BC1TL offset (cc = 0 implied)
BC1TL cc, offset
Purpose: To test an FP condition code and do a PC-relative conditional
branch; execute the delay slot only if the branch is taken.
-----------------------------------------------------------------
| C.cond.fmt| floating-point Compare |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | cc |00 |11 | cond |
------6----------5---------5---------5-------3----2---2-----4----
cond: 0000 = F (False)
0001 = UN (Unordered)
0010 = EQ (Equal)
0011 = UEQ (Unordered or Equal)
0100 = OLT (Ordered or Less Than)
0101 = ULT (Unordered or Less Than)
0110 = OLE (Ordered or Less than or Equal)
0111 = ULE (Unordered or Less than or Equal)
1000 = SF (Signaling False)
1001 = NGLE (Not Greater than or Less than or Equal)
1010 = SEQ (Signaling Equal)
1011 = NGL (Not Greater than or Less than)
1100 = LT (Less Than)
1101 = NGE (Not Greater than or Equal)
1110 = LE (Less than or Equal)
1111 = NGT (Not Greater Than)
Format: C.cond.S fs, ft
C.cond.D fs, ft
Purpose: To compare FP values and record the Boolean result in
a condition code.
-----------------------------------------------------------------
| CEIL.L.fmt| floating-point CEILing convert to Long fixed-point|
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001010 (10)|
------6----------5---------5---------5---------5----------6------
Format: CEIL.L.S fd, fs
CEIL.L.D fd, fs
Purpose: To convert an FP value to 64-bit fixed-point, rounding up.
-----------------------------------------------------------------
| CEIL.W.fmt| floating-point CEILing convert to Word fixed-point|
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001110 (14)|
------6----------5---------5---------5---------5----------6------
Format: CEIL.W.S fd, fs
CEIL.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point, rounding up.
-----------------------------------------------------------------
| CFC1 | Move control word From Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00010 (2)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: CFC1 rt, fs
Purpose: To copy a word from an FPU control register to a GPR.
Descrip: rt = fs
-----------------------------------------------------------------
| CTC1 | Move control word To Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00110 (6)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: CTC1 rt, fs
Purpose: To copy a word from a GPR to an FPU control register.
Descrip: fs = rt
-----------------------------------------------------------------
| CVT.D.fmt | floating-point ConVerT to Double floating-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |100001 (33)|
------6----------5---------5---------5---------5----------6------
Format: CVT.D.S fd, fs
CVT.D.W fd, fs
CVT.D.L fd, fs
Purpose: To convert an FP or fixed-point value to double FP.
-----------------------------------------------------------------
| CVT.L.fmt | floating-point ConVerT to Long fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |100101 (37)|
------6----------5---------5---------5---------5----------6------
Format: CVT.L.S fd, fs
CVT.L.D fd, fs
Purpose: To convert an FP value to a 64-bit fixed-point.
-----------------------------------------------------------------
| CVT.S.fmt | floating-point ConVerT to Single floating-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |100000 (32)|
------6----------5---------5---------5---------5----------6------
Format: CVT.S.D fd, fs
CVT.S.W fd, fs
CVT.S.L fd, fs
Purpose: To convert an FP or fixed-point value to single FP.
-----------------------------------------------------------------
| CVT.W.fmt | floating-point ConVerT to Word fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |100100 (36)|
------6----------5---------5---------5---------5----------6------
Format: CVT.W.S fd, fs
CVT.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point.
-----------------------------------------------------------------
| DIV.fmt | floating-point DIVide |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | fd | 000011 (3)|
------6----------5---------5---------5---------5----------6------
Format: DIV.S fd, fs, ft
DIV.D fd, fs, ft
Purpose: To divide FP values.
-----------------------------------------------------------------
| DMFC1 | Doubleword Move From Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00001 (1)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: DMFC1 rt, fs
Purpose: To copy a doubleword from an FPR to a GPR.
-----------------------------------------------------------------
| DMTC1 | Doubleword Move To Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00101 (5)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: DMTC1 rt, fs
Purpose: To copy a doubleword from a GPR to an FPR.
-----------------------------------------------------------------
|FLOOR.L.fmt| floating-point FLOOR convert to Long fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001011 (11)|
------6----------5---------5---------5---------5----------6------
Format: FLOOR.L.S fd, fs
FLOOR.L.D fd, fs
Purpose: To convert an FP value to 64-bit fixed-point, rounding down.
-----------------------------------------------------------------
|FLOOR.W.fmt| floating-point FLOOR convert to Word fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001111 (15)|
------6----------5---------5---------5---------5----------6------
Format: FLOOR.W.S fd, fs
FLOOR.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point, rounding down.
-----------------------------------------------------------------
| LDC1 | Load Doubleword to Floating-Point |
|-----------|---------------------------------------------------|
|110101 (53)| base | ft | offset |
------6----------5---------5-------------------16----------------
Format: LDC1 ft, offset(base)
Purpose: To load a doubleword from memory to an FPR.
Descrip: COP ft = doubleword[base+offset]
-----------------------------------------------------------------
| LWC1 | Load Word to Floating-Point |
|-----------|---------------------------------------------------|
|110001 (49)| base | ft | offset |
------6----------5---------5-------------------16----------------
Format: LWC1 ft, offset(base)
Purpose: To load a word from memory to an FPR.
Descrip: COP ft = word[base+offset]
-----------------------------------------------------------------
| MFC1 | Move Word From Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00000 (0)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: MFC1 rt, fs
Purpose: To copy a word from an FPU (CP1) general register to a GPR.
Descrip: rt = COP fs
-----------------------------------------------------------------
| MOV.fmt | floating-point MOVe |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 000110 (6)|
------6----------5---------5---------5---------5----------6------
Format: MOV.S fd, fs
MOV.D fd, fs
Purpose: To move an FP value between FPRs.
-----------------------------------------------------------------
| MTC1 | Move Word to Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00100 (4)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: MTC1 rt, fs
Purpose: To copy a word from a GPR to an FPU (CP1) general register.
Descrip: COP fs = rt
-----------------------------------------------------------------
| MUL.fmt | floating-point MULtiply |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | fd | 000010 (2)|
------6----------5---------5---------5---------5----------6------
Format: MUL.S fd, fs, ft
MUL.D fd, fs, ft
Purpose: To multiply FP values.
-----------------------------------------------------------------
| NEG.fmt | floating-point NEGate |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 000111 (7)|
------6----------5---------5---------5---------5----------6------
Format: NEG.S fd, fs
NEG.D fd, fs
Purpose: To negate an FP value.
-----------------------------------------------------------------
|ROUND.L.fmt| floating-point ROUND to Long fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 001000 (8)|
------6----------5---------5---------5---------5----------6------
Format: ROUND.L.S fd, fs
ROUND.L.D fd, fs
Purpose: To convert an FP value to 64-bit fixed-point, rounding to nearest.
-----------------------------------------------------------------
|ROUND.W.fmt| floating-point ROUND to Word fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001100 (12)|
------6----------5---------5---------5---------5----------6------
Format: ROUND.W.S fd, fs
ROUND.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point, rounding to nearest.
-----------------------------------------------------------------
| SDC1 | Store Doubleword from Floating-Point |
|-----------|---------------------------------------------------|
|111101 (61)| base | ft | offset |
------6----------5---------5-------------------16----------------
Format: SDC1 ft, offset(base)
Purpose: To store a doubleword from an FPR to memory.
Descrip: doubleword[base+offset] = COP rt
-----------------------------------------------------------------
| SQRT.fmt | floating-point SQuare RooT |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 000100 (4)|
------6----------5---------5---------5---------5----------6------
Format: SQRT.S fd, fs
SQRT.D fd, fs
Purpose: To compute the square root of an FP value.
-----------------------------------------------------------------
| SUB.fmt | floating-point SUBtract |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | fd | 000001 (1)|
------6----------5---------5---------5---------5----------6------
Format: SUB.S fd, fs, ft
SUB.D fd, fs, ft
Purpose: To subtract FP values.
-----------------------------------------------------------------
| SWC1 | Store Word from Floating-Point |
|-----------|---------------------------------------------------|
|111001 (57)| base | ft | offset |
------6----------5---------5-------------------16----------------
Format: SWC1 ft, offset(base)
Purpose: To store a word from an FPR to memory.
Descrip: word[base+offset] = COP rt
-----------------------------------------------------------------
|TRUNC.L.fmt| floating-point TRUNCate to Long fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 001001 (9)|
------6----------5---------5---------5---------5----------6------
Format: TRUNC.L.S fd, fs
TRUNC.L.D fd, fs
Purpose: To convert an FP value to 64-bit fixed-point, rounding toward zero.
-----------------------------------------------------------------
|TRUNC.W.fmt| floating-point TRUNCate to Word fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001101 (13)|
------6----------5---------5---------5---------5----------6------
Format: TRUNC.W.S fd, fs
TRUNC.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point, rounding toward zero.
---------------------------------------------------------
Resources:
R4300i documentation from MIPS Technologies, Inc.
R4000 Instructions from Silicon Graphics
Project UnReality by Michael Tedder
Disa64 by TRILILI
Nintendo 64 opcodes
Part C: R4300 Command set released on 98-02-19
----------------------------------------------------------------------------
****************************************************************************
** Main CPU **
****************************************************************************
CPU: Instructions encoded by opcode field.
31---------26---------------------------------------------------0
| opcode | |
------6----------------------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | *1 | *2 | J | JAL | BEQ | BNE | BLEZ | BGTZ |
001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI |
010 | *3 | *4 | *5 | | BEQL | BNEL | BLEZL | BGTZL |
011 | DADDI |DADDIU | LDL | LDR | | | | |
100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU |
101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE |
110 | LL | LWC1 | LWC2 | | LLD | LDC1 | LDC2 | LD |
111 | SC | SWC1 | SWC2 | | SCD | SDC1 | SDC2 | SD |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
*1 = SPECIAL, see SPECIAL list *2 = REGIMM, see REGIMM list
*3 = COP0 *4 = COP1 *5 = COP2
SPECIAL: Instr. encoded by function field when opcode field = SPECIAL.
31---------26------------------------------------------5--------0
| = SPECIAL | | function|
------6----------------------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | SLL | | SRL | SRA | SLLV | | SRLV | SRAV |
001 | JR | JALR | | |SYSCALL| BREAK | | SYNC |
010 | MFHI | MTHI | MFLO | MTLO | DSLLV | | DSRLV | DSRAV |
011 | MULT | MULTU | DIV | DIVU | DMULT | DMULTU| DDIV | DDIVU |
100 | ADD | ADDU | SUB | SUBU | AND | OR | XOR | NOR |
101 | | | SLT | SLTU | DADD | DADDU | DSUB | DSUBU |
110 | TGE | TGEU | TLT | TLTU | TEQ | | TNE | |
111 | DSLL | | DSRL | DSRA |DSLL32 | |DSRL32 |DSRA32 |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
REGIMM: Instructions encoded by the rt field when opcode field = REGIMM.
31---------26----------20-------16------------------------------0
| = REGIMM | | rt | |
------6---------------------5------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | BLTZ | BGEZ | BLTZL | BGEZL | | | | |
01 | TGEI | TGEIU | TLTI | TLTIU | TEQI | | TNEI | |
10 | BLTZAL| BGEZAL|BLTZALL|BGEZALL| | | | |
11 | | | | | | | | |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
****************************************************************************
** COP0 **
****************************************************************************
COP0: Instructions encoded by the fmt field when opcode = COP0.
31--------26-25------21 ----------------------------------------0
| = COP0 | fmt | |
------6----------5-----------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | MFC0 | DMFC0 | CFC0 | | MTC0 | DMTC0 | CTC0 | |
01 | *1 | | | | | | | |
10 | *2 | | | | | | | |
11 | | | | | | | | |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
*1 = BC instr, see BC0 list *2 = TLB instr, see TLB list
BC0: Instructions encoded by the nd and tf fields when opcode
= COP0 and fmt = BC.
31--------26-25------21 ---17--16-------------------------------0
| = COP0 | = BC | |nd|tf| |
------6----------5-----------1--1--------------------------------
|---0---|---1---| tf
0 | BC0F | BC0T |
1 | BC0FL | BC0TL |
nd |-------|-------|
TLB: Instructions encoded by the function field when opcode
= COP0 and fmt = TLB.
31--------26-25------21 -------------------------------5--------0
| = COP0 | = TLB | | function|
------6----------5-----------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | | TLBR | TLBWI | | | | TLBWR | |
001 | TLBP | | | | | | | |
010 | | | | | | | | |
011 | ERET | | | | | | | |
100 | | | | | | | | |
101 | | | | | | | | |
110 | | | | | | | | |
111 | | | | | | | | |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
****************************************************************************
** COP1 - Floating Point Unit **
****************************************************************************
COP1: Instructions encoded by the fmt field when opcode = COP1.
31--------26-25------21 ----------------------------------------0
| = COP1 | fmt | |
------6----------5-----------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | MFC1 | DMFC1 | CFC1 | | MTC1 | DMTC1 | CTC1 | |
01 | *1 | | | | | | | |
10 | *2 | *3 | | | *4 | *5 | | |
11 | | | | | | | | |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
*1 = BC instructions, see BC1 list
*2 = S instr, see FPU list *3 = D instr, see FPU list
*4 = W instr, see FPU list *5 = L instr, see FPU list
BC1: Instructions encoded by the nd and tf fields when opcode
= COP1 and fmt = BC
31--------26-25------21 ---17--16-------------------------------0
| = COP1 | = BC | |nd|tf| |
------6----------5-----------1--1--------------------------------
|---0---|---1---| tf
0 | BC1F | BC1T |
1 | BC1FL | BC1TL |
nd |-------|-------|
FPU: Instructions encoded by the function field when opcode = COP1
and fmt = S, D, W or L
31--------26-25------21 ----------------------------------------0
| = COP1 | = S | |
------6----------5-----------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | ADD | SUB | MUL | DIV | SQRT | ABS | MOV | NEG |
001 |ROUND.L|TRUNC.L| CEIL.L|FLOOR.L|ROUND.W|TRUNC.W| CEIL.W|FLOOR.W|
010 | | | | | | | | |
011 | | | | | | | | |
100 | | CVT.D | | | CVT.W | CVT.L | | |
101 | | | | | | | | |
110 | C.F | C.UN | C.EQ | C.UEQ | C.OLT | C.ULT | C.OLE | C.ULE |
111 | C.SF | C.NGLE| C.SEQ | C.NGL | C.LT | C.NGE | C.LE | C.NGT |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
31--------26-25------21 ----------------------------------------0
| = COP1 | = D | |
------6----------5-----------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | ADD | SUB | MUL | DIV | SQRT | ABS | MOV | NEG |
001 |ROUND.L|TRUNC.L| CEIL.L|FLOOR.L|ROUND.W|TRUNC.W| CEIL.W|FLOOR.W|
010 | | | | | | | | |
011 | | | | | | | | |
100 | CVT.S | | | | CVT.W | CVT.L | | |
101 | | | | | | | | |
110 | C.F | C.UN | C.EQ | C.UEQ | C.OLT | C.ULT | C.OLE | C.ULE |
111 | C.SF | C.NGLE| C.SEQ | C.NGL | C.LT | C.NGE | C.LE | C.NGT |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
31--------26-25------21 ----------------------------------------0
| = COP1 | = W, L | |
------6----------5-----------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | | | | | | | | |
001 | | | | | | | | |
010 | | | | | | | | |
011 | | | | | | | | |
100 | CVT.S | CVT.D | | | | | | |
101 | | | | | | | | |
110 | | | | | | | | |
111 | | | | | | | | |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
Nintendo 64 opcodes
Part D: ROM header released on 98-02-19
----------------------------------------------------------------------------
* Mr Backup Z64 (.BIN or .Z64 files) uses a Low/High byte format
(Little Endian), wich is the "correct" format to read from.
* Doctor V64 (.V64, .N64 or .U64 files) uses a High/Low byte format
(Big Endian), so each word are byte flipped, like this:
"ETTSNI G"
When it should look like this:
"TESTING "
To solve this, rotate the word to left/right by 8 bits.
----------------------------------------------------------------------------
The addresses below is only valid for ROM's in Low/High
format, eg: Mr Backup Z64 ROM's. You have to byteswap Doctor
V64 ROM's before you can read data that makes any sense.
----------------------------------------------------------------------------
0000h - 0001h (1 word): 8037h
Can be used to validate ROM, if the word is
mirrored, it means that you have a byteswapped
ROM image to deal with.
0002h (1 byte): Is ROM image compressed or not? (RTool standard)
12h = Uncompressed
13h = Compressed
0003h - 0008h (5 bytes): 400000000Fh
0008h - 000Ch (1 dword): Game address (also called Entry point)
I don't know what this is for, as the
Game code always starts at 1000h.
000Ch - 000Fh (3 bytes): 000014h
000Fh (1 byte): Don't know the meaning of this byte.
44h (Darkrift, Fire demo)
46h (Waverace64)
48h (Bomber64, Duke64, TetPal)
0010h - 0014h (1 dword): CRC1
0014h - 0018h (1 dword): CRC2
0018h - 001Fh (8 bytes): 0000000000000000h
0020h - 0033h (20 bytes): Image name
Padded with 00h or spaces (20h)
0034h - 003Ah (7 bytes): 00000000000000h
003Bh (1 byte): Manufacturer ID
4Eh 'N' = Nintendo
003Ch - 003Dh (2 bytes): Cartridge ID
003Eh (1 byte): Country code
44h 'D' = Germany
45h 'E' = USA
4Ah 'J' = Japan
50h 'P' = Europe
55h 'U' = Australia (maybe)
003Fh (1 byte): 00h
0040h - 0FFFh (1008 dword): Boot code starts here.
Pretty much the same code on most of
the ROM's, Starfox64 differs.
1000h (rest of file): Game code starts here.
R4300 Data Sheet, Rev 0.3, April 1997 1
R4300i MICROPROCESSOR
Description
The R4300i is a low-cost RISC microprocessor optimized for demanding consumer applications. The R4300i provides
performance equivalent to a high-end PC at a cost point to enable set-top terminals, games and portable consumer devices.
The R4300i is compatible with the MIPS R4000 family of RISC microprocessors and will run all existing MIPS software.
Unlike its predecessors designed for use in workstations, the R4300i is expected to lower the cost of systems in which it is
used, a requirement for price-sensitive consumer products. The R4300i is also an effective embedded processor, supported
by currently available development tools and providing very high performance at a low price-point.
Overview
The success of the MIPS R3000 processor and its derivatives has established the MIPS architecture as an attractive
high-performance choice in emerging consumer applications such as interactive TV and games. The R4300i is the 64-bit
successor to the R3000 for this class of applications. It is specifically designed to be extremely low-cost from the outset, yet
supply the performance necessary for full interactivity.
The R4300i achieves its low-cost goal by holding to a very small die size, simple package and low testing costs. It is
further enabled for consumer applications by easily interfacing to other low-cost components. Its low power consumption
also reduces system cost by combining high clock speed with limited power drawn, saving on power supply and heat
dissipation costs.
mips
Open RISC Technology
R4300i MICROPROCESSOR
PRODUCT INFORMATION
Addr/Data Controls
32-bit System Interface
Co-Processor
0
Instruction
Address
Pipeline
Control
Clk Gen
MasterClock
64-bit
Unit
Execution
8kB
Data
Cache
16kB
Instruction
Cache
Features
Low Power Dissipation:
• 1.8W (normal)
High Performance at 100MHz:
• 60 SPECint92
• 45 SPECfp92
High bandwidth interface:
• Max throughput 250MB/s
• 32-bit address/data bus
• 4-deep flush buffers
High integration on-chip:
• 16K I-cache, 8K D-cache
• Unified datapath
• 32 double-entry J-TLB
• 2 entry micro I-TLB
Power Management Features:
• Reduced Power Mode
• Instant On/Off
R4000 family compatibility:
• R4000 software compatible
• Runs Windows NT/UNIX
Consumer Applications
Set-top terminals
Game systems
Personal Digital Assistants
Embedded Applications
X-terminals
Laser printers
Factory automation
Networking: routers, bridges
Graphics acceleration
Packaging
R4300i (120-pin PQFP)
2 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
Overview (cont.)
The R4300i has a number of design features to reduce
power. These include an all-dynamic design, unified integer
and floating-point datapath, a reduced power mode of
operation, and caches partitioned into separate banks.
Printers, networking devices and other embedded
applications will also benefit from the high performance,
low cost and high-bandwidth interface of the R4300i. The
R4300i is the next standard in low-cost processing in the
MIPS Microprocessor family.
R4300i Architecture
Data Format
The R4300i defines a 64-bit double-word, a 32-bit word,
a 16-bit halfword and an 8-bit byte. The byte ordering is
configurable in either Big-endian or Little-endian format.
Figures 1 and 2 show the ordering of bytes for Big-endian
and Little-endian conventions
.
Figure 1 Big-endian Byte Alignment
Figure 2 Little-endian Byte Alignment
Processor Resources
The R4300i CPU provides sixty-four 64-bit wide
registers. Thirty-two of these registers, referred to as
General Purpose Register (GPRs), are reserved for integer
operations while the other thirty-two register, referred to as
Floating Point General Purpose Register (FGRs), are
reserved for floating point operations. These two register
sets are shown in Figure 3.
Figure 3 General Purpose Registers
The width of these registers depends on the mode of
operation. In 32-bit mode, they are treated as 32 bits wide.
In 64-bit mode, they are treated as 64 bits wide.
The R4300i also contains six special registers: the
program counter (PC), multiply/divide result Hi and Lo,
Load/Link (LL) bit, and floating point Implementation and
Control registers FCR0 and FCR31; shown in Figure 4. The
program counter register contains the address of the
current instruction. The multiply/divide registers store the
result of integer multiply operations and the quotient and
remainder of integer divide operations. The load/link bit is
dedicated for load-link and store-conditional instructions
which can be used to perform SYNC operations. The two
floating point control registers, FCR0 and FCR31, provide
the implementation/revision information and
control/status of the floating point coprocessor (CP1).
Figure 4 Special Registers
In addition, the R4300i operates with up to three
tightly coupled coprocessors (designated CP0 through
CP2). Coprocessor zero (CP0) is implemented as an
integral part of the CPU and supports the virtual memory
system together with exception handling. Coprocessor one
(CP1) is reserved for the floating point unit, while
coprocessor two is reserved for future use.
Coprocessor zero contains registers shown in Figure 5
plus a 32-entry TLB with each entry consisting of an
even/odd pair of physical addresses and tag field.
31 24 23 16 15 8 7 0
byte-0 byte-1 byte-2 byte-3
byte-4 byte-5 byte-6 byte-7
byte-8 byte-9 byte-A byte-B
byte-C byte-D byte-E byte-F
Word
Address
C
8
4
0
High
Addr
Low
Addr Most significant byte is at lowest address
Word is addressed by byte address of most significant byte
31 24 23 16 15 8 7 0
byte-3 byte-2 byte-1 byte-0
byte-7 byte-6 byte-5 byte-4
byte-B byte-A byte-9 byte-8
byte-F byte-E byte-D byte-C
Word
Address
C
8
4
0
High
Addr
Low
Addr Least significant byte is at lowest address
Word is addressed by byte address of least significant byte
63 32 31 0
r0
r1
r2
r30
r31
General Purpose Regs (GPRs)
63 32 31 0
FGR0
FGR1
FGR2
FGR30
FGR31
FP General Purpose Regs (FGRs)
63 32 31 0
PC
Program Counter (PC)
63 32 31 0
MultHI
MultLO
Multiply/Divide Registers
31 0
FCR0
FCR31
Floating Point
Impl/Rev
Control/Status
Registers
0
LLbit
3 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
.
Figure 5 Coprocessor-0 Registers
The CP0 registers can be considered as two distinct
functional sets. The first set comprises those which support
the TLB operations. The second set is formed from those
registers that reflect the status of the processor. All of the
CP0 registers are accessible by software.
Instruction Set
All R4300i instructions are 32 bits (single word) long
aligned on word boundaries, as shown in Figure 6.
Figure 6 Instruction Formats
This approach simplifies instruction decoding. More
complicated operations and addressing modes are
synthesized by the compiler. There are three instruction
formats: I-type (immediate), J-type (jump), and R-type
(register).
Load and Store instructions move data between
memory and the general registers. They are all immediate
(I-type) instructions. The only addressing mode that load
and store instructions directly support is base register plus
16-bit signed extended immediate offset.
Load and store instruction opcodes determine the
access type which indicates the size of the data item to be
loaded or stored. Regardless of the access type or
byte-numbering order (endianness), the address field
specifies the lowest byte of the address location being
accessed.
Computational instructions perform arithmetic,
logical, shift, multiply, and divide operations on values in
registers. They occur in both register (R-Type) format, in
which both operands are registers, and immediate (I-Type)
format, in which one operand is a 16-bit immediate. When
operating in 64-bit mode, 32-bit operands must be correctly
sign extended.
Jump and branch instructions change the control flow of
a program. They occur in both register (R-Type) format, and
immediate (I-Type) format. All jump and branch
instructions occur with an architecture delay of one
instruction; that is, the instruction immediately following
the jump or branch is always executed while the target
instruction is being fetched.
Special instructions allow the software to initiate traps
and are always R-Type.
Exception instructions offer a trapping mechanism to
assist in software debug.
Coprocessor instructions perform operations in the
respective coprocessors. Coprocessor loads and stores are
I-type, and coprocessor computational instructions have
coprocessor dependent formats.
Pipeline
The R4300i processor has a five-stage execution
pipeline, as shown in Figure 7. Each pipeline stage takes
one pclock to execute. The frequency of pclock can be either
1, 1.5, 2, or 3 times the frequency of the MasterClock,
depending on the state of DivMode 1:0 signals. The
execution of each instruction thus has a latency of at least
five pcycles. Once the pipeline has been completely filled,
five instructions are always being executed simultaneously.
When the pipeline is not stalled, the processor has a
throughput of one instruction per pcycle. The pipeline is
in-order issue, in-order execution, and in-order completion,
the same order as in the instruction stream.
PageMask
5*
EntryHi
10*
EntryLo0 2*
EntryLo1 3*
Index
0*
Random
1*
Wired
6*
Context
4*
Count
9*
TagHi
29*
WatchHi
19*
SR
12*
CacheErr
27*
EPC
14*
Config
16*
BadVAddr
8*
Compare
11*
TagLo
28*
WatchLo
18*
Cause
13*
PErr
26*
ErrEPC
30*
PRId
15*
LLAddr
17*
Safe Entries Safe Entries
EVEN
ENTRIES
ODD
ENTRIES
CP0
REGISTERS
XContext
20*
31 26 25 21 20 16 15 0
11 10 6 5
26
6
Op code rs rt Immediate
31 26 25 0
Op code target
31 26 25 21 20 16 15 0
Op code rs rt
5 5 16
6 5 5 5 5
6
6
rd sa funct
I-Type (Immediate)
R-Type (Register)
J-Type (Jump)
Op code is a 6-bit operation code
rs is a 5-bit source register specifier
rt is a 5-bit target register specifier
immediate is a 16-bit immediate, branch displacement or
address displacement
target is a 26-bit jump target address
rd is a 5-bit destination register specifier
sa is a 5-bit shift amount
funct is a 5-bit function field
4 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
Figure 7 Pipeline Activities
The five stages of the R4300i pipeline are: Instruction
Cache (IC), Instruction Decode and Register File Read (RF),
Execution (EX), Data Cache Read (DC), and Register File or
Data Cache Write Back (WB). Figure 7 shows the activities
occurring during each pipeline stage for ALU, load and
store, and branch instructions. Below are detail descriptions
of the activities during each stage.
IC: An instruction address is presented by the
address unit and the instruction cache fetch
begins. The instruction micro-TLB starts the
virtual-to-physical address translation.
RF: The instruction becomes available and the
instruction decoder decodes the instruction and
checks for interlock conditions. The instruction
cache tag is checked against the page frame
number obtained from the micro-TLB. Any
required operands are read from the register file
and the result from the EX or DC stages is
bypassed to the following EX stage if required.
The address unit generates the next instruction
address.
EX: For ALU class instructions, the ALU performs an
arithmetic or logical operation. For load and
store class instructions, the ALU generates the
data virtual address. For branch instructions, the
ALU determines whether the branch condition is
true.
DC: For load and store instructions, the data cache is
accessed and data virtual-to-physical address
translation is performed. At the end of the DC
stage, the data becomes available and the
load-align shifts the data to a word or
double-word boundary. In addition, the data
cache tag is checked against the page frame
number obtained from the joint TLB.
WB: For register-to-register or load instructions, the
result is written back to the register file. For store
instructions, the data cache is updated with the
store data.
The R4300i has a branch delay of one cycle and a load
delay of one cycle. The branch delay is observed by noting
that the branch compare logic operates during the EX
pipestage, producing the target address which is available
for the IC pipestage of the second subsequent instruction.
The first subsequent instruction is the instruction in the
delay slot and will be allowed to complete whether the
branch is taken or not, as illustrated in Figure 8.
Figure 8 Branch Delay Slot
Similarly, the load delay of one is evident when the
completion of a load at the end of the DC pipeline stage
produces an operand which is available for the EX
pipestage of the second subsequent instruction. The load
delay is illustrated in Figure 9.
.
Figure 9 Load Delay Slot
Hardware detects whether the instruction in the branch
delay slot is dependent on the register to be loaded, and
interlocks accordingly.
The pipeline flow is interrupted when an interlock
condition is detected or when an exception occurs. An
interlock condition is resolved by stalling the whole
IC RF EX DC WB
F1 F2 F1 F2 F1 F2 F1 F2 F1 F2
ITLB ITC
ICF IDEC
RFR
ALU
DVA
BCMP
IVA
DTLB DTC
DCR LA RFW
RFW
DCW
Instr. Fetch
Instr. Decode
Reg. File Read
Arithmetic/Logical
Operations
PClock
Load/Store
Operations
Jump/Branch
Operations
Phase
Cycle
Cycle Phase Mnemonic Descriptions
IC
F1 No activity
F2 ICF
ITLB
Instruction Cache Fetch
Instruction micro-TLB read
RF
F1 ITC Instruction cache Tag Check
F2
RFR
IDEC
IVA
Register File Read
Instruction Decode
Instruction Virtual Address Calculation
EX
F1
BCMP
ALU
DVA
Branch Compare
Arithmetic Logic Operation
Data Virtual Address Calculation
F2 No new activity started
DC
F1 DCR
DTLB
Data Cache Read
Data TLB look-up
F2 LA
DTC
Load Data Alignment
Data Cache Tag Check
WB
F1 DCW
RFW
Data Cache Write
Register File Write
F2 No activity
IC RF EX DC WB
IC RF EX DC WB
IC RF EX DC WB
beq r2, r3, target
addi r2, 1
target: ld r4, (r5)
branch delay slot
instruction
instruction
branch instruction
target
IC RF EX DC WB
IC RF EX DC WB
IC RF EX DC WB
ld r2, (r4)
addi r4, 4
add r2, r6
load delay slot
from DC to EX pipestage
load instruction
load data is bypassed
5 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
pipeline. On the other hand an exception aborts the relevant
instruction and all those that follow.
Figure 10 illustrates the various interlock conditions
and the different types of exceptions, at their pre-defined
pipeline stages.
Figure 10 Pipeline Interlocks and Exceptions
In the case of simultaneous stall requests from different
pipestages, the pipeline control unit prioritizes which stall
request is allowed to be resolved, in case of possible
resource conflict. A stall request from the DC pipestage has
higher priority than a stall request from the RF pipestage.
Execution Unit
The execution unit is designed to reduce power
consumption and simplify the hardware requirements
while providing a high level of performance by maximizing
usage of each functional element. Integer performance is
optimized for the R4300i’s target applications.
The execution unit is tightly coupled to the on-chip
cache memory system, instruction and data caches, and the
on-chip memory management unit, CP0. This unit has a
multifunction pipe and is responsible for the execution of:
• Integer arithmetic and logic instructions
• Floating-point Coprocessor CP1 instructions
• Branch/Jump instructions
• Load/Store instructions
• Exception instructions
• Special instructions
All floating-point instructions, as defined in the MIPS
ISA for the floating-point coprocessor CP1, are processed by
the same hardware as used for the integer instructions.
However, the execution of floating-point instructions can
still be disabled via the “Coprocessor Unusable” CU bit
defined in the CP0 Status register.
The execution unit uses a modular design approach to
further reduce dynamic power consumption. Control logic
is partitioned into small independent blocks responsible for
a set of instructions. When relevant instructions are not in
the instruction stream, the corresponding control blocks
become inactive. Also, when functional elements in the
datapath are idle, they operate on a constant (0’s or 1’s)
selected to minimize power dissipation.
The execution unit’s datapath consists of: a 64-bit
integer/mantissa datapath, an operand bypass network, 32
64-bit integer registers, 32 64-bit floating-point registers, a
12-bit exponent datapath, and a 64-bit instruction virtual
address generator.
As shown in Figure 11, the integer/mantissa datapath
is 64 bits wide and is compatible with both 32-bit and 64-bit
operands for integer and floating-point numbers. It has a
Boolean Logic functional unit, a Carry-Propagate Adder, a
CSA Multiplier, and a bi-directional Shifter.
The Logical Operation unit performs all integer logical
operations. The carry-propagated adder is used for all other
integer and floating-point computational instructions. The
adder is also used to compute data virtual address for load
and store instructions, and to compare two operands in trap
instructions. The CSA multiplier is used for both integer
and floating-point multiplication, in single or double
precision. The shifter is responsible for integer variable
shifts, store align shifts, and floating-point
post-normalization. It also has build-in
guard/round/sticky collection logic for floating-point
pre-alignment shift. In addition, the datapath has a Leading
Zero Counter for floating-point normalization shift
calculation, and a floating-point unpacker and repacker.
IC RF EX DC WB
F1 F2 F1 F2 F1 F2 F1 F2 F1 F2
PClock
Phase
Cycle
Pipe Interlock Conditions
Descriptions Descriptions
ITM Instruction TLB Miss ICB Instruction Cache Busy
LDI Load Interlock MCI Multi-Cycle Interlock
CPI Coprocessor-2 Interlock DCB Data Cache Busy
COp Cache Op DCM Data Cache Miss
CP0I CP0 Bypass Interlock
Pipe Exception Conditions
Descriptions Descriptions
IADE Instruction Address Error OVFL Integer Overflow
ITLB Instruction TLB Miss TRAP TRAP Exception
IBE Instruction Bus Error FPE Floating Point Exception
SYSC System Call Instruction CPE Coprocessor-2 Exception
CPU Coprocessor Unusable DAE Data Address Error
RSVD Reserved Instruction DTLB Data TLB Exception
RST External Reset Exception DBE Data Bus Error
NMI Non-Maskable Interrupt INTR External Interrupt
BRPT BreakPoint Instruction WAT Reference Watch Address
Stalls
Exceptions
ITM
ICB
LDI
MCI
CPI
DCM
DCB
COp
IADE
ITLB
IBE
SYSC
BRPT
CPU
RSVD
RST
NMI
OVFL
TRAP
FPE
CPE
DAE
DTLB
WAT
DBE
INTR
CP0I
R4300 Data Sheet, Rev 0.3, April 1997 6
R4300i MICROPROCESSOR
Figure 11 Integer/Mantissa Datapath
Figure 12 Exponent Datapath
COMBINED REGISTER FILE
SIGN EXTEND
UNPACK
SIGN EXTEND
UNPACK
SIGN EXTEND
RS RT
BYPASS MUX BYPASS MUX
CARRY-PROPAGATE ADDER SHIFTER
RESULT MUX
SUM REG
LOGICAL
OPERATION
RMUX
OPMUX
LOAD ALIGNER
DBUS
SIGN EXTEND
REPACK
DVA1DC
BYPASS NETWORK IMMEDIATE
WB REG
X Y
Z
CSA
BLOCK
MULTIPLIER
SHIFT MUX SHIFT MUX SHIFT MUX
FEEDBACK MUX
ES MUX
CARRY-SELECT ADDER
ET MUX
S T
EXPONENTS FROM
UNPACKER
UnpExpS UnpExpT
Leading Zero Cnt
RESULT MUX
Cin=1 Cin=0
EXP SUM REG
TO REPACK LOGIC
Result Check
SR1 0 1
Constant Gen
Underflow
Overflow
One
Zero
> One
Convert Limit Chk
7 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
For load and store class instructions, the datapath can
handle partial-words in either big- or little-endian mode.
For store instructions, the main bi-directional shifter
performs an alignment shift on the register read data. No
concatenation of register read data with the original
memory data is necessary since the data cache has byte
write enable controls. For load instructions, it is necessary to
maintain a load delay of one pclock cycle. Due to the timing
requirements imposed by this load delay, a dedicated
byte-wide shifter (Load Aligner) is needed to shift the
memory read data in bytes, halfwords, and words in the
right or left direction.
The operand bypass network is built into the datapath
to allow feedback of results from the EX and DC pipeline
stages to the instructions in the following EX pipestage
waiting to use the results as source operands rs and/or rt.
This allows the following instruction to proceed without
having to wait for the results to be written back to the
register file. Similarly, to maintain the minimum branch
delay slot of one pipeline clock cycle for all branch
instructions on the floating-point condition, the results from
the preceding floating-point compare instruction in the EX,
DC, or WB pipestage will be fed back for branch condition
testing in the RF pipestage.
The exponent datapath is 12 bits wide. The twelfth bit
(MSB) is used as both sign bit and overflow bit. The
exponent datapath consists of a feedback mux and 2
operand muxes to select the inputs from the adder, constant
generating logic, a carry select adder, random logic to
perform exception detection, and a register to hold the
selected result from the adder, as shown in Figure 12.
The inputs to the exponent unit come from the unpack
logic, where the exponents are extracted from single- or
double-precision floating-point operands. The
carry-selected adder performs exponent subtraction,
pre-alignment shift calculation, and exponent addition for
post-normalization final update. The result is sent to the
repack logic to be merged with the mantissa.
The result of the exponent logic is compared with
constants or ranges to check for various conditions by the
result checker. These conditions include: underflow,
overflow in single-precision number, overflow in
double-precision number, one, zero, and convert limit
check. The checks are performed as soon as data is available
from the carry-select adder.
The instruction virtual address unit is responsible for
the generation of 64-bit instruction virtual addresses to be
used by the micro-TLB, I-Cache and CP0. It has its own
incrementor to calculate the next sequential address. It also
has an equality comparator and a separate ripple-carry
adder to generate the branch target address.
In addition, the address unit has exception vector
generator logic to decode the type of exception and then
present the appropriate vector as the next PC address. It
also has the exception PC register pipe chain to maintain a
history of PC addresses for each pipestage so that the PC
address associated with the exception causing instruction
can be loaded into the Exception Program Counter (EPC)
register.
Cache Organization
To achieve high performance, increase memory access
bandwidth and reduce the latency of load and store
instructions, the R4300i processor incorporates on-chip
instruction and data caches. Each cache has its own 64-bit
datapath and can be accessed in parallel with the other
cache. Both the instruction and data caches are direct
mapped, virtually indexed, and use physical tags. The
R4300i cache organization is shown in Figure 13.
Figure 13 R4300i Cache Organization
The instruction cache is 16 kilobytes in size. It is
organized as eight-word (32-byte) lines with a 21-bit tag
entry associated with each line. The tag entry consists of a
valid bit (V), and a 20-bit physical tag (bit 31:12 of the
physical address). The format of an instruction cache line is
shown in Figure 14.
Figure 14 R4300i Instruction Cache Line Form
D-Cache I-Cache
Data-Path/
Flush-Buffer
SysAD Output Data Path
Control
SysAD Input
Data Path
PAD Ring
SysAD Bus
Cache
Cntl
DTAG ITAG
DBus IBus
64
64 64
32
20 19 0
1 20
V Physical TAG Data
Data
Data
Data
31 0
Data
Data
Data
Data
where:
V Valid bit
PTAG 20 bit physical tag (bit 31:12 of the physical address)
Data Data word
32
8 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
An instruction cache line has two possible cache states:
Invalid and Valid. A cache line with invalid cache state does
not contain valid information. A cache line in a valid state
contains valid information.
The instruction cache is accessible in one p-cycle.
Access begins on phase 2 of the IC pipestage and completes
at the end of phase 1 of the RF pipestage. Each access will
fetch two instructions. Therefore instruction fetching is
required only on every other run cycle or when there is a
jump/branch instruction in the EX pipestage. When there is
a miss detected during an instruction cache access, a
memory block read will be initiated from the system
interface to replace the current cache line with the desired
line.
The data cache is 8 kilobytes in size. It is organized as
four-word (16-byte) lines with a 22-bit tag entry associated
with each line.The tag entry consists of a valid bit (V), a
dirty bit (D), and a 20 bit physical tag (bit 31:12 of the
physical address). The format of a data cache line is shown
in Figure 15.
Figure 15 R4300i Data Cache Line Format
A data cache line has three possible cache states:
invalid, valid clean, and valid dirty. A data cache line with
an invalid state does not contain valid information. A cache
line in valid clean state contains valid information and is
consistent with main memory. A cache line in valid dirty
state contains valid data but is not consistent with main
memory. Figure 16 illustrates the data cache state transition
sequence.
Figure 16 R4300i Data Cache State Transition
The data cache uses a write-back cache policy. This
means that store data is written to the cache line rather than
main memory. The modified cache line will be written back
to main memory only when it needs to be replaced. For load
or store misses, a cache block read will be issued to main
memory to bring in a new line and the missed line will be
handled in the following manner:
Data load miss:
• If the missed line is not dirty, it will be replaced
with the new line.
• If the missed line is dirty, the missed line will be
moved to the flush-buffer, the new line will
replaced the missed line, and the data in the
flush-buffer will be written back to main memory.
Data store miss:
• If the missed line is not dirty, it will be replaced
with the new line.
• If the missed line is dirty, the missed line will be
moved to the flush-buffer, the new line will be
written to the cache, and the data in the
flush-buffer will be written back to main memory.
• In either store miss case, the store data is merged
with the new line.
The data cache is accessible on reads in one p-cycle. The
access begins on phase 1 of the DC pipestage and completes
at the end of phase 2 of the DC pipestage. Each access will
fetch a double word. The data cache writes, however,
execute in two p-cycles. A cache read is initiated in the first
p-cycle, and a cache write with dirty bit set is initiated in the
second p-cycle.
The data cache can be accessed for byte, half-word,
three-byte, word, five-byte, six-byte, seven-byte, and
double-word. The data size of a partial load is derived from
the access type from the integer control unit and the lower
three address bits. The data alignment is performed by the
datapath load aligner.
To reduce the cache miss penalty, the address of the
block read request will point to the location of the desired
double-word. Since the data cache has a two double-word
line size, the system interface will return the critical
double-word first, followed by the remaining double-word.
The return data will be written to the cache as it is put on the
data bus to be used by the execution unit.
The R4300i processor provides a variety of cache
operations for use in maintaining the state and contents of
the instruction and data caches. During the execution of the
cache operation instructions, the processor may issue
processor block read or write request to fill or write-back a
cache line.
Flush Buffer
The R4300i Microprocessor contains a 4-entry on-chip
flush buffer. The buffer is used as temporary data storage
for outgoing data and is organized as a 4 deep fifo; that is it
can buffer 4 addresses along with 4 double-words of data.
For uncached write operations, the flush buffer can accept
21 20 19 0
1 1 21
V Physical TAG Data
Data
Data
Data
31 0
32
D
where:
V Valid bit
D Dirty Bit
PTAG 20 bit physical tag (bits 31:12 of the physical address)
Data Data word
Invalid
Clean
Valid
Read
Store
Read
Read Miss
Store
Read Hit,
Store.
Cache-op Cache-op
Cache-op
Valid
Dirty
9 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
any combination of single or double-word data until it is
full, with each write occupying one entry in the buffer. For
data cache block write operations, the flush buffer accepts 2
double-words with 1 address, occupying two entries in the
buffer. It is able to take two block references at a time.
Instruction cache block writes use 4 doublewords with 1
address. Instruction cache block writes occupy the entire
flush buffer. The flush buffer is able to take one read
memory reference at a time.
Address is a 32-bit physical address, and size indicates
the size of data to be transferred out.
During an uncached store, data will be stored in this
buffer until it is taken by the external interface. While data
awaits in this area, processor pipeline continues to execute.
During a load miss or a store miss to a cache line in the
dirty state, a read request for the missing cache line is sent
to the external interface. The dirty data is then stored in the
flush buffer until the requested data is returned from the
external interface. The processor pipeline continues to run
while the flush buffer writes the dirty data to the external
interface.
If the flush buffer is full and the processor attempts a
load or a store which requires external resources, the
processor pipeline will stall until the buffer is emptied.
Figure 17 shows the layout of the flush buffer.
Figure 17 Flush Buffer Format
Coprocessor 0
The R4300i Coprocessor-0 functional unit performs two
major functions. The first is memory management for the
processor, and the second is exception processing. CP0 is
logically divided into four subunits: CP0 Register Files
(Cp0reg), Translation Look-aside Buffer (TLB), Instruction
TLB (ITLB), and CP0 Control Unit (Cp0ctl). Figure 18 shows
how these subunits interact with each other and other
functional units.
The CP0 registers consist of two functionally distinct
sets. The first set comprises those that support the TLB
operations, and the second set is formed from those
registers that reflect the state of the processor. All of the CP0
registers are readable by software. All but the Random,
BadVAddr, PrId, and MskId registers are writable by
software. The definitions of the CP0 registers are described
in a later section.
The CP0ctl subunit controls data transfer to and from
the TLB, ITLB and CP0 registers. It takes the instruction
decode signals from the integer unit and interprets them to
determine whether a CP0 register is to be read or written. It
generates control signals for reading and writing TLB and
ITLB entries.
Figure 18 R4300i Coprocessor 0 Block Diagram
In addition, the CP0ctl handles exception processing. Its
function is to communicate with the pipeline control unit
for interrupt signalling, and notification of TLB exceptions.
It also performs address checking with regard to the type of
instruction being executed, and various state bits in the
Status register. For example, a User mode process may try to
access a kernel data address. In this case, a Data Address
Error exception would be detected, since the address
Region bits would conflict with the KSU bits in the Status
register.
The Translation Look-aside Buffers (micro-TLB and
joint TLB) are responsible for the translation of both
instruction and data virtual addresses into physical
addresses. The physical address is needed by the cache for
its tag checks, and by the system interface for off-chip
memory access, and various CP0 registers. The jTLB
translates the lower 40 bits of the 64-bit virtual address size
defined in the MIPS-III architecture, and provides a 32-bit
physical address.
The joint TLB contains 32 entries, each of which is
simultaneously checked for a match with the extended
virtual address. Each TLB entry maps an even-odd pair of
pages. The page size is 4K, 16K, 64K, 256K, 1M, 4M or 16M
bytes, which is specified on a per-entry basis by the MASK
bit-mask field of the entry. The valid values of the MASK
field and the effect on the translation is documented in the
description of the PageMask register.
A virtual address matches a TLB entry when the virtual
page number (VPN) field of the virtual address equals the
VPN field of the TLB entry, and either the Global (G) bit of
where:
R/W Read/Write
Size Transfer Size Field
Address Flush Buffer Address
Data Flush Buffer Data
R/W Size Address Data
1 4 32 64
ITLB
TLB
CP0REG
CP0CTL
IVA
DVA
INDEX
ENHI
ENLO
TLBMISS
ADDR CHK
TAG
DATA
I-PFN
D-PFN
EXCEPTIONS
STATUS
DBUS
CACHE DATA
INTERRUPTS
10 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
the TLB entry is set or the address space identifier (ASID)
field of the virtual address (as held in the EntryHi register)
matches the ASID field of the TLB entry. Although the valid
(V) bit of the entry must be set for a valid translation to take
place, it is not involved in the determination of a matching
TLB entry.
The operation of the TLB is not defined if more than one
entry in the TLB matches. If one TLB entry matches, the
physical address and access control bits (N, D, and V) are
retrieved; otherwise a TLB refill exception occurs. If the
access control bits (D and V) indicate that the access is not
valid, a TLB modification or TLB invalid exception occurs.
The format of a TLB entry in 32-bit addressing mode is
shown in Figure 19.
Figure 19 TLB Entry Format in 32-bit Addressing Mode
The format of a TLB entry in 64-bit mode is shown in
Figure 20.
Figure 20 TLB Entry Format in 64-bit Addressing Mode
The R4300i also implements a two entry micro-TLB that
is dedicated for instruction address translation. This allows
instruction address translation to be done simultaneously
with data address translation. If there is a miss in the
micro-TLB, the pipeline will stall while the new TLB entry
is transferred from the joint TLB to the micro-TLB. The two
entry micro-TLB entry is fully associative with a Least
Recently Used replacement algorithm. Each micro-TLB
entry maps to a 4K byte page size only.
CP0 Registers
Table 1 lists all CP0 registers used in the R4300i.
Attempting to write any unused register is undefined and
may have an unpredictable effect on the R4300i processor.
Attempting to read any unused register is undefined and
may result in unpredictable data.
The Index register is a read/write register in which 6 bits
specify an entry into the on-chip TLB. The high order bit
indicates the success or failure of a TLBP operation. The
TLB Index register is used to specify the entry in the TLB
affected by the TLBR and TLBWI instructions. Figure 21
shows the Index register format.
Figure 21 Index Register
31 25 24 6 5 3 2 1 0
127 121 120 109 108 96
63 57 56 38 37 35 34 33 32
- MASK -
95 77 76 75 72 71 64
VPN2 G - ASID
- PFN (even) C D V -
- PFN (odd) C D V -
6 19 3 1 1 1
6 19 3 1 1 1
19 1 4 8
7 12 13
- MASK -
VPN2 G - ASID
- PFN (even) C D V -
- PFN (odd) C D V -
255 217 216 205 204 192
189 168 167 141 140 139 136 135 128
R
191 190
127 89 88 70 69 67 66 65 64
63 25 24 6 5 3 2 1 0
38 19 3 1 1 1
38 19 3 1 1 1
2 22 27 1 4 8
39 12 13
Where:
R Is the Region used to match VAddr63..62
MASK is the comparison MASK
VPN2 is the Virtual Page Number / 2
G Global bit
ASID Address Space Identifier
PFN Physical Page Number (upper 20 bits of the physical address)
C Cache Algorithm (011=cached; 010=uncached)
D If set, page is writable
V If set, entry is valid
Table 1 System Control Coprocessor 0 Registers
Num Mnemonic Descriptions
0 Index Programmable pointer into TLB array
1 Random Random pointer into TLB array
2 EntryLo0 Low half of the TLB entry for even VPN
3 EntryLo1 Low half of the TLB entry for odd VPN
4 Context Pointer to kernel PTE table
5 PageMask TLB page mask
6 Wired Number of wire TLB entries
7 ---- Unused
8 BadVAddr Bad virtual address
9 Count Timer count
10 EntryHi High half of TLB entry
11 Compare Timer compare
12 SR Status register
13 Cause Cause register
14 EPC Exception program counter
15 PRid Processor revision identifier
16 Config Configuration register
17 LLAddr Load linked address
18 WatchLo Memory reference trap address lower bits
19 WatchHi Memory reference trap address upper bits
20 XContext Context register for MIPS-III addressing
21-25 ---- Unused
26 PErr Not Used
27 CacheErr Not Used
28 TagLo Cache tag register
29 TagHi Cache tag register (Reserved)
30 ErrorEPC Error exception program counter
31 ---- Unused
31 30 65 0
P 0 Index
1 25 6
where:
P Result of last Probe operation. Set to 1 if last TLB Probe
instruction was unsuccessful
index Index to entry in TLB
0 Must be all zeroes on reads and writes
11 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
The Random register is a read-only register in which 6
bits specify an entry in the on-chip TLB. This register will
decrement on every instruction executed. The values range
between a low value determined by the TLB Wired register,
and an upper bound of TLBENTRIES-1. The TLB Random
register is used to specify the entry in the TLB affected by
the TLBWR instruction. Upon system reset, or when the
Wired register is written, this register will be set to the upper
limit. Figure 22 shows the Random register format.
Figure 22 CP0 Random Register
The EntryLo0 and EntryLo1 registers are a read/write
register pair that are used to access on-chip TLB. EntryLo0 is
used for the even virtual pages while EntryLo1 is used for
the odd virtual pages. They contain the Page Frame
Number, along with several configuration bits for the TLB
entry. They are used by the TLBR, TLBWI, and TLBWR
instructions. Figure 23 shows the EntryLo0 and EntryLo1
registers format.
Figure 23 CP0 EntryLo0 and EntryLo1 Registers
The Context register is a read/write register containing
a pointer into a kernel Page Table Entry (PTE) array. It is
designed for use in the TLB refill handler. The BadVPN2
field is not writable. It contains the VPN of the most recently
translated virtual address that did not have a valid
translation. It contains bits 31:13 of the virtual address that
caused the TLB miss. Bit 12 is excluded because a single TLB
entry maps an even-odd page pair. This format can be used
directly as an address for pages of size 4K bytes. For all
other page sizes the value must be shifted and masked. The
PTEBase field is writable as well as readable, and indicates
the base address of the PTE table of the current user address
space. Figure 24 shows the Context register format.
Figure 24 CP0 Context Register
The PageMask register is a read/write register that is
used when reading or writing an on-chip TLB. The TLBR,
TLBWI, and TLBWR instructions use this register as a
source or destination.When virtual addresses are presented
for translation, the corresponding bits in the TLB specify
which of virtual address bits 24.13 participate in the
comparison. This implements a variable page size on a per
entry basis. R4300i implements 4K, 16K, 64K, 256K, 1M, 4M
and 16M pages. Figure 25 shows the PageMask register
format.
.
Figure 25 CP0 Mask Register
The TLB Wired register is a read/write register that
specifies the boundary between the wired and random
entries of the TLB. This register is set to 0 upon reset.
Writing to this register also sets the Random register to 31.
Writing a value greater than TLBENTRIES-1 to this register
will result in undefined behavior. Figure 26 shows the Wired
register.
Figure 26 CP0 Wired Register
31 65 0
0 Random
26 6
where:
Random Index to entry in TLB
0 Must be all zeroes on reads and writes
31 30 6 5 0
0 PFN C
2 24 3
where:
PFN Physical Frame Number
C Cache Algorithm. If C=011, then page is cached. If
C=010, then it is uncached. All other values of C are
cached.
V Page Valid if 1, invalid if 0
G If set in both Lo0 and Lo1, then ignore ASID
0 Must be zero on all reads and writes
D Page Dirty if 1, Clean if 0
29
D V G
1 1 1
3 2 1
63 30 6 5 0
0 PFN C
34 24 3
29
D V G
1 1 1
3 2 1
32 bit Mode:
64 bit Mode:
31 23 4 0
PTEBase BadVPN2
9 19 4
where:
PTEBase Base address of the Page Entry Table
BadVPN2 Virtual Page Number of the failed virtual address
divided by two
0 Must be zero on reads and writes
3
32 bit Mode:
64 bit Mode:
22
0
63 23 4 0
PTEBase BadVPN2
41 19 4
22 3
0
31 25 13 0
0 MASK
7 12 13
where:
MASK Mask for Virtual Page Number. For R4300i, this is
0000_0000_0000 for 4K pages, 0000_0000_0011 for 16K
pages and so on up to 111111111111 for 16M pages.
0 Must be zero on reads and writes
24 12
0
31 6 0
0
26 6
where:
Wired TLB wired boundary
0 Must be zero on reads and writes
5
Wired
12 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
The Bad Virtual Address register is a read-only register
that displays the most recently translated virtual address
which failed to have a valid translation or which had an
addressing error. Figure 27 shows the BadVAddr register
format.
Figure 27 CP0 BadVAddr Register
The Count register is a read/write register used to
implement timer services. It increments at a constant rate
based on the clock cycle. On R4300ii, it will increment at
one-half the PClock speed. When the Count register has
reached all ones, it will roll over to all zeroes and continue
counting. This register is both readable and writable. It is
writable for diagnostic purposes. Figure 28 shows the Count
register format.
Figure 28 CP0 Count Register
The EntryHi register is a read/write register that is used
to access on-chip TLB. It is used by the TLBR, TLBWI, and
TLBWR instructions. EntryHi contains the Address Space
Identifier (ASID) and the Virtual Page Number. Figure 29
shows the EntryHi register format.
Figure 29 CP0 EntryHi Register
The Compare register is a read/write register. When the
value of the Count register equals the value of the Compare
register, IP7 of the Cause register is set. This causes an
interrupt on the next execution cycle in which interrupt is
enabled. Writing to the Compare register will clear the timer
interrupt. Figure 30 shows the Compare register format.
Figure 30 CP0 Compare Registers
The Status register is a read/write register that contains
the various mode, enables, and status bits used on R4300i.
The contents of this register are undefined after a reset,
except for TS, which is zero; ERL and BEV, which are one;
and RP, which is zero. The SR bit is 0 after a Cold Reset, and
1 after NMI or (Soft) Reset. Figure 31 shows the Status
register format.
Figure 31 CP0 Status Register
31 0
BadVAddr
32
where:
BadVAddr Most recently translated virtual address that failed to
have a valid translation or that had an addressing
error.
32 bit Mode:
64 bit Mode:
63 0
BadVAddr
64
31 0
32
where:
Count Current count value, updated at 1/2 Pclock Frequency
Count
31 8 0
VPN2
19 8
where:
R Region (00=user, 01=supervisor,11=kernel) used to
match vAddr63..62
FILL Reserved; undefined on read, should be 0 or -1 on
write (should sign extend the virtual page number)
VPN2 Virtual Page Number divided by 2
0 Must be zero on reads and writes
ASID Address Space Identifier
7
32 bit Mode:
64 bit Mode:
0
13 12
ASID
5
63 8 0
VPN2
27 8
7
0
13 12
ASID
5
62 61 40 39
2 22
R FILL
31 0
32
where:
Compare Value to be compared to Count register. An interrupt
will be signaled when they are equal.
Compare
31 28
CU
4 1
where:
CU Coprocessor Unit usable if 1. CP0 is always usable by
the kernel
RP Reduced Power. Changes clock to quarter speed.
FR If set, enables MIPS III additional floating point
registers.
RE Reverse Endian. Changes endianness in user mode.
ITS Instruction Trace Support. Enables trace support.
rsvd Reserved for future use.
BEV Controls location of TLB refill and general exception
vectors. (0=normal, 1= bootstrap).
TS TLB Shutdown has occurred.
SR Soft Reset or NMI has occurred.
0 Must be zeroes on read and write.
CH This is the CP0 Condition bit. It is readable and
writable by software only. It is not set or cleared by
hardware.
CE, DE These fields are included to maintain compatibility.
with the R4200 and are not used in the R4300i.
IM Interrupt Mask. Enables and disables interrupts.
KX Kernel extended addressing enabled.
SX Supervisor extended addressing enabled.
UX User extended addressing enabled.
KSU Mode (10=user, 01=supervisor, 00=kernel)
ERL Error Level. Normal when zero, error if one
EXL Exception Level. Normal when zero, exception if one
IE Interrupt Enable.
1 1 1
RP FR RE ITS rsvd BEV TS SR 0 CH CE DE
27 26 25 24 23 22 21 20 19 18 17 16
1 1 1 1 1 1 1 1
15
IM
2 1 1 1
KX SX UX KSU ERLEXL IE
8 7 6 5 4 3 2 1 0
8 1 1 1
13 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
The Cause register is a read/write register that describes
the nature of the last exception. A five-bit exception code
indicates the cause of the exception and the remaining fields
contain detailed information relevant to the handling of
certain types of exceptions. The Branch Delay bit indicates
whether the EPC has been adjusted to point at the branch
instruction which precedes the next restartable instruction.
The Coprocessor Error field indicates the unit number
referenced by an instruction causing a “Coprocessor
Unusable” exception. The Interrupt Pending field indicates
which interrupts are pending. This field indicates the
current status and changes in response to external signals.
IP7 is the timer interrupt bit, set when the Count register
equals the Compare register. IP6:2 are the external interrupts,
set when the external interrupts are signalled. An external
interrupt is set at one of the external interrupt pins or via a
write request on the SysAD bus. IP1:0 are software
interrupts, and may be written to set or clear software
interrupts. Figure 32 shows the Cause register format.
Figure 32 CP0 Cause Register
The EPC register is a read/write register that contains
the address at which instruction processing may resume
after servicing an exception. For synchronous exceptions,
the EPC register contains either the virtual address of the
instruction which was the direct cause of the exception, or
when that instruction is in a branch delay slot, the EPC
contains the virtual address of the immediately preceding
branch or jump instruction and the Branch Delay bit in the
Cause register is set. If the exception is caused by
recoverable, temporary conditions (such as a TLB miss), the
EPC contains the virtual address of the instruction which
caused the exception. Thus, after correcting the conditions,
the EPC contains a point at which execution can be
legitimately resumed. Figure 33 shows the format of EPC
register.
Figure 33 CP0 EPC Register
The PRId register is a read-only register that contains
information that identifies the implementation and revision
level of the processor and associated system control
coprocessor. The revision number can distinguish some
chip revisions. However, MIPS is free to change this register
at any time and does not guarantee that changes to its chips
will necessarily change the revision number, or that changes
to the revision number necessarily reflect real chip changes.
For this reason, software should not rely on the revision
number to characterize the chip. Figure 34 shows the
Processor Revision Identifier register format.
Figure 34 CP0 Revision Identifier Register
The Config register specifies various configuration
options that are available for R4300i. It is compatible with
the R4000 Config register, but only a small subset of the
options available on the R4000 are possible on R4300i. For
that reason, there are many fields which are set to constant
values. The EP and BE fields are writable by software only.
The CU and K0 fields are readable and writable by software.
There is no other mechanism for writing to these fields, and
their values are undefined after Reset. Figure 35 shows the
Configuration register format.
where:
BD Branch Delay
CE Coprocessor Error
IP Interrupt pending
ExcCode Exception Code:
0 Must be zeroes on read and write
0 Int Interrupt
1 Mod TLB modification exception
2 TLBL TLB Exception (Load or instruction
fetch)
3 TLBS TLB Exception (Store)
4 AdEL Address Error Exception (Load or
instruction fetch)
5 AdES Address Error Exception (Store)
6 IBE Bus Error Exception (instruction
fetch)
7 DBE Bus Error Exception (data reference:
load or store)
8 Sys SysCall Exception
9 Bp Breakpoint Exception
10 RI Reserved instruction Exception
11 CpU Coprocessor Unusable Exception
12 Ov Arithmetic Overflow Exception
13 Tr Trap Exception
14 --- Reserved
15 FPE Floating Point Exception
16-22 Reserved
23 Watch Reference to WatchHi/WatchLo
address
24-31 Reserved
31
0
2 1 5 2
IP ExcCode 0
8 76 210
11 12
BD 0 CE 0
30 29 28 27 16 15
8
31 0
EPC
32
where:
EPC Exception Program Counter.
32 bit Mode:
64 bit Mode:
63 0
EPC
64
31 0
16
where:
Imp Implementation identifier: 0x0B for R4300i
Rev Revision Number
0 Returns zeroes on reads.
0 Imp Rev
16 15 8 7
8 8
14 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
Figure 35 CP0 Configuration Register
The R4300ii processor provides a debugging feature to
detect references to a physical address. Loads or stores to
the location specified by the WatchHi/WatchLo register pair
cause a Watch trap. Figure 36 shows WatchHi/WatchLo
register formats.
Figure 36 CP0 WatchLo and WatchHi Registers
The LLAddr register contains the physical address read
by the most recent Load Linked instruction. This register
exists for diagnostic purposes, and serves no function
during normal operation. It is both readable and writable by
software. Figure 37 shows the LLAddr register format.
Figure 37 CP0 LLAddr Register
The XContext register is a read/write register
containing a pointer into a kernel Page Table Entry (PTE)
array. It is designed for use in the XTLB refill handler. The R
and BadVPN2 fields are not writable. The register contains
the VPN of the most recently translated virtual address that
did not have a valid translation. It contains bits 39.13 of the
virtual address that caused the TLB miss. Bit 12 is excluded
because a single TLB entry maps an even-odd page pair.
This format can be used directly as an address for pages of
size 4K bytes. For all other page sizes this value must be
shifted and masked. The PTEBase field is writable as well as
readable, and indicates the base address of the PTE table of
the current user address space. Figure 38 shows XContext
register format.
Figure 38 CP0 XContext Register
The PErr register, shown in Figure 39, is included only
to maintain compatibility with the R4200. The R4300i does
not implement parity, hence this register is not used by
hardware. However, the register is software readable and
writable.
Figure 39 CP0 PErr Register
31 28
EP
4 1
where:
EC System Clock Ratio: Read only
110 = 1:1
111 = 1.5:1
000 = 2:1
001 = 3:1
All other values of EC are undefined.
EP Pattern for writeback data on SYSAD port
0000 -> D
0110 -> DxxDxx
All other values of EP are undefined.
BE BigEndianMem
0 -> Memory and kernel are Little Endian
1 -> Memory and kernel are Big Endian
CU Reserved. (Read- and Writ-able by software)
K0 Kseg0 coherency algorithm. This has the same format
as the C field in EntryLo0 and EntryLo1. The only
defined values for K0 for R4300i are 010
(noncacheable) and 011 (cacheable).
0 Returns 0 on read.
1 Returns 1 on read.
1 3
0000 01 B 0 010 001 1 0 C K0
27 24 23 20 8 6 5 4 3 2 0
4 4 2 1 1111
EC 1
19 18 1716 15 14 13 12 11 9
0 1 1
1 3 3 1
E U
30
0
31 0
where:
PAddr Physical address
WatchLo PAddr contains bits 31.3
In the R4300i bits 3:0 of the WatchHi register
are ignored but are software writable. This
is to maintain compatibility with the R4000.
R Trap on Read Access if 1
W Trap on Write Access if 1
0 Must be zeroes on reads and writes
PAddr
31 0
31
PAddr
4
0
WatchLo:
WatchHi:
R W
1
0
3 2 1
29 1 1
4
3
31 0
where:
Paddr Bits 35..4 of the physical address. Note that for R4300i,
the MSB of the physical address is only 31. A load
linked instruction will write 0 into bits[31..29] of
LLAddr, but a software write can set all 32 bits to any
value. This maintains compatibility with R4000.
PAddr
63 4 0
PTEBase BadVPN2
31 27
where:
PTEBase Base address of the Page Entry Table
BadVPN2 Virtual Page Number of the failed virtual address
divided by two
R Region (00=user, 01=supervisor, 11=kernel)
0 Must be zero on reads and writes
3
R 0
3332 31 30
2 4
31 8 0
0
24 8
where:
Diagnostic Eight bit diagnostic field
0 Must be zeroes on all reads and writes
7
Diagnostic
15 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
The CacheErr register, shown in Figure 40, is included
only to maintain compatibility with the R4200. The R4300i
does not implement cache errors, hence this register is not
used by hardware. It is a read only register which returns a
zero value when read.
Figure 40 CP0 CacheErr Register
The TagLo register is a 32-bit read/write register used to
hold the cache tag during cache initialization and
diagnostics. The TagHi register is reserved for future use.
These two Tag registers are written by the CACHE and
MTC0 instructions. Figure 41 shows TagLo and TagHi
register formats.
Figure 41 CP0 TagLo TagHi Registers
The ErrorEPC register is similar to the EPC, but is used
to store the PC on Reset and NMI exceptions. It is
read/write register and contains the virtual address at
which instruction processing may resume after servicing an
Error or Reset/NMI exceptions.
The EPC register contains either the virtual address of
the instruction which was the direct cause of the exception,
or when that instruction is in a branch delay slot, the EPC
contains the virtual address of the immediately preceding
branch or jump instruction. There is no branch delay slot
indication for ErrorEPC. Figure 42 shows ErrorEPC register
format.
Figure 42 CP0 ErrorEPC Register
Memory Management
The R4300i processor provides a full-featured memory
management unit (MMU) which uses an on-chip
translation look-aside buffer (TLB) to translate virtual
address into physical address. The TLB is a fully associative
memory that holds 32 entries, which provide mapping to 32
odd/even pairs (64 pages). When address mapping is
indicated, each TLB entry is checked simultaneously for a
match with the virtual address that is extended with an
ASID stored in the EntryHi register. The address is mapped
to a page of size of between 4Kbytes and 16Mbytes.
The processor virtual address can be either 32 or 64 bits
wide, depending on whether the processor is operating in
32-bit or 64-bit mode.
• In 32-bit mode, addresses are 32 bits wide. The
maximum user process size is 2 gigabytes (231).
• In 64-bit mode, addresses are 64 bits wide. The
maximum user process size is 1 terabyte (240).
Figure 43 shows the translation of a virtual address into
a physical address.
Figure 43 Virtual-to-Physical Address Translation
31 0
0
31 0
where:
PTagLo Physical address bits 31.12
Pstate Primary Cache State (0=invalid, 3=Dirty)
0 Must be zeroes on reads and writes
PTagLo
31 0
32
TagHi = 0
TagLo:
TagHi:
0 0
20 6
28 27
4
6 5
PState
8 7
2
31 0
ErrorEPC
32
ErrorEPC Exception Program Counter for Reset and NMI.
32 bit Mode:
64 bit Mode:
63 0
Error EPC
64
1. Virtual address (VA) represented
by the virtual page number
(VPN) is compared with tag in
TLB.
Virtual address
2. If there is a match, the page frame
number (PFN) representing the
upper bits of the physical
address (PA) is output from the
TLB.
VPN
TLB
Physical address
Offset
TLB
3. The Offset, which does not pass
through the TLB, is then
concatenated to the PFN.
Entry
G ASID
G ASID VPN
EVEN PFN
ODD PFN
PFN Offset
16 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
Converting a virtual address to a physical address
begins by comparing the virtual address from the processor
with the virtual address in the TLB; there is a match when
the virtual page number (VPN) of the address is the same as
the VPN field of the entry, and either:
• the Global (G) bit of the TLB entry is set, or
• the ASID field of the virtual address is the same as
the ASID field of the TLB entry.
This match is referred to as a TLB hit. If there is no
match, a TLB Miss exception is taken by the processor and
software is allowed to refill the TLB from a page table of
virtual/physical addresses in memory.
If there is a virtual address match in the TLB, the
physical address is output from the TLB and concatenated
with the Offset, which represents an address within the page
frame space.
Figure 44 shows the virtual-to-physical address
translation of a 32-bit mode address.
Figure 44 32-Bit-Mode Virtual Address Translation
• The top portion of Figure 44 shows a virtual
address with a 12-bit, or 4-Kbyte, page size,
labelled Offset. The remaining 20 bits of the address
represent the VPN, and index the 1M-entry page
table.
• The bottom portion of Figure 44 shows a virtual
address with a 24-bit, or 16-Mbyte, page size,
labelled Offset. The remaining 8 bits of the address
represent the VPN, and index the 256-entry page
table.
Figure 45 shows the virtual-to-physical-address
translation of a 64-bit mode address. This figure illustrates
the two possible page sizes: a 4-Kbyte page (12 bits) and a
16-Mbyte page (24 bits).
• The top portion of Figure 45 shows a virtual
address with a 12-bit, or 4-Kbyte, page size,
labelled Offset. The remaining 28 bits of the address
represent the VPN, and index the 256M-entry page
table.
• The bottom portion of Figure 45 shows a virtual
address with a 24-bit, or 16-Mbyte, page size,
labelled Offset. The remaining 16 bits of the
address represent the VPN, and index the
64K-entry page table.
Figure 45 64-Bit-Mode Virtual Address Translation
The processor has three operating modes that function
in both 32- and 64-bit operations: User mode, Supervisor
mode, and Kernel mode. The address space for each mode
of operation are described in the following sections.
In User mode, a single, uniform virtual address
space—labelled User segment—is available; its size is:
• 2 Gbytes (231 bytes) in 32-bit mode (useg)
• 1 Tbyte (240 bytes) in 64-bit mode (xuseg)
The User segment starts at address 0 and the current
active user process resides in either useg (in 32-bit mode) or
xuseg (in 64-bit mode). The TLB identically maps all
references to useg/xuseg from all modes, and controls cache
accessibility*. Figure 46 shows User mode virtual address
space.
* The cached (C) field in a TLB entry determines whether
the reference is cached; see Figure 20.
28 11 0
20 12
39 3231 29
8
Virtual Address with 1M (220) 4-Kbyte pages
23 0
8 24
Offset
39
Virtual Address with 256 (28)16-Mbyte pages
8 bits = 256 pages
20 bits = 1M pages 12
ASID
8
3231 2928
VPN
24
Virtual-to-physical
translation in TLB
Bits 31, 30 and 29 of the
virtual address select user,
supervisor, or kernel
address spaces.
Offset passed
unchanged to
physical
memory
Virtual-to-physical
translation in TLB
TLB
TLB
31 0
PFN Offset
Offset passed
unchanged to
physical
memory
32-bit Physical Address
ASID VPN Offset
11 0
12
63
VPN Offset
71 64
ASID
8
Mapped Virtual Address with 256M (228) 4-Kbyte pages
23 0
24 24
Offset
Virtual Address with 64K (216)16-Mbyte pages
16 bits = 64K pages
28 bits = 256M pages 12
ASID VPN
62 61 40 39
28
0 or -1
71 64 63 62 61 40 24
8
39
16
24
0 or -1
Virtual-to-physical
translation in TLB
Virtual-to-physical
translation in TLB TLB
31 0
PFN Offset
TLB
Offset passed
unchanged to
physical
memory
Offset passed
unchanged
physical memory
32-bit Physical Address
17 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
Figure 46 User Mode Virtual Address Space
The processor operates in User mode when the Status
register contains the following bit-values:
• KSU bits = 102
• EXL= 0
• ERL= 0
In conjunction with these bits, the UX bit in the Status
register selects between 32- or 64-bit User mode addressing
as follows:
• when UX = 0, 32-bit useg space is selected
• when UX = 1, 64-bit xuseg space is selected
Supervisor mode is designed for layered operating
systems in which a true kernel runs in R4300i Kernel mode,
and the rest of the operating system runs in Supervisor
mode. Figure 47 shows Supervisor mode address space.
Figure 47 Supervisor Mode Virtual Address Space
The processor operates in Supervisor mode when the
Status register contains the following bit-values:
• KSU= 012
• EXL= 0
• ERL= 0
In conjunction with these bits, the SX bit in the Status
register selects between 32- or 64-bit Supervisor mode
addressing:
• when SX = 0, 32-bit supervisor space is selected
• when SX = 1, 64-bit supervisor space is selected
The processor operates in Kernel mode when the Status
register contains one of the following values:
• KSU= 002
• EXL= 1
• ERL= 1
In conjunction with these bits, the KX bit in the Status
register selects between 32- or 64-bit Kernel mode
addressing:
• when KX = 0, 32-bit kernel space is selected
• when KX = 1, 64-bit kernel space is selected
The processor enters Kernel mode whenever an
exception is detected and it remains in Kernel mode until an
Exception Return (ERET) instruction is executed. The ERET
instruction restores the processor to the mode existing prior
to the exception.
Kernel mode virtual address space is divided into
regions differentiated by the high-order bits of the virtual
address, as shown in Figure 48.
Figure 48 Kernel Mode Virtual Address Space
useg xuseg
Address
Error
1 TB
Mapped
32-bit 64-bit
0x FFFF FFFF FFFF FFFF
0x 0000 0000 0000 0000
0x FFFF FFFF
0x 8000 0000
0x 0000 0000
0x 0000 0100 0000
Address
Error
Mapped
2 GB
0000
2 GB
Mapped
Mapped
suseg
Address
0.5 GB
error
sseg
Address
error
Address
error
Mapped
xsuseg
Address
0.5 GB
error
1 TB xsseg
Mapped
Address
error
32-bit 64-bit
csseg
0x FFFF FFFF FFFF FFFF
0x 4000 0100 0000 0000
0x 0000 0000 0000 0000
0x FFFF FFFF E000 0000
0x FFFF FFFF C000 0000
0x 4000 0000 0000 0000
0x 0000 0100 0000 0000
0x FFFF FFFF
0x 8000 0000
0x 0000 0000
0x E000 0000
0x C000 0000
0x A000 0000
Address
error
1 TB
Mapped 2 GB
0.5 GB
0.5 GB
Mapped
Mapped
Unmapped
Unmapped
kuseg
kseg0
kseg1
0.5 GB
0.5 GB
Mapped
ksseg
kseg3
Uncached
Cached
32-bit*
0x FFFF FFFF
0x 8000 0000
0x 0000 0000
0x E000 0000
0x C000 0000
0x A000 0000
xkuseg
ckseg0
ckseg1
xksseg
Mapped ckseg3
0.5 GB
Mapped
0.5 GB
0.5 GB
Unmapped
Uncached
0.5 GB
Unmapped
Cacheable
Address
error
cksseg
1 TB
Mapped
Mapped xkseg
xkphys
64-bit
Address
error
0x FFFF FFFF FFFF FFFF
0x 4000 0100 0000 0000
0x 0000 0000 0000 0000
0x FFFF FFFF E000 0000
0x FFFF FFFF C000 0000
0x 4000 0000 0000 0000
0x 0000 0100 0000 0000
0x 9000 0000 0000 0000
0x C000 0000 0000 0000
0x FFFF FFFF A000 0000
0x FFFF FFFF 8000 0000
0x C000 00FF 8000 0000
1 TB
Mapped
0x 9000 0002 0000 0000
Address
error
Unmapped xkphys
0x 9800 0000 0000 0000 Cached
0x 9800 0002 0000 0000
Address
error
Address
error
Unmapped
Uncached
18 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
Exception Management
The R4300i processor receives exceptions from a
number of sources, including translation lookaside buffer
(TLB) misses, arithmetic overflows, I/O interrupts, and
system calls. When the CPU detects one of these exceptions,
the normal sequence of instruction execution is suspended
and the processor enters Kernel mode.
The processor then disables interrupts and forces
execution of a software exception processor (called a
handler) located at a fixed address. The handler saves the
context of the processor, including the contents of the
program counter, the current operating mode (User or
Supervisor), and the status of the interrupts (enabled or
disabled). This context is saved so it can be restored when
the exception has been serviced.
When an exception occurs, the CPU loads the Exception
Program Counter (EPC) register with a location where
execution can restart after the exception has been serviced.
The restart location in the EPC register is the address of the
instruction that caused the exception or, if the instruction
was executing in a branch delay slot, the address of the
branch instruction immediately preceding the delay slot.
The R4300i separates exceptions into four vector spaces:
Reset and NMI vector, TLB Refill vector, XTLB Refill vector,
and General exception vector. The values of each vector
(except Reset and NMI) depend on the Boot Exception
Vector (BEV) bit of the Status register, which allow two
alternate sets of vectors to be used, with one set pointing to
the PROM address space and the other set point to
cacheable address space.
The Reset and NMI exceptions are always vectored to
location 0xBFC0 0000 in 32-bit mode, and location 0xFFFF
FFFF BFC0 0000 in 64-bit mode.
The addresses for all other exceptions are a combination
of a vector offset and a base address. The base address is
determined by the BEV bit of the Status register. Table 2
shows the exception R4300i exception vectors.
While more than one exception can occur for a single
instruction, only the exception with the highest priority is
reported. Table 3 lists all exceptions in the order of their
priority.
Exceptions are logically precise. The instruction that
causes an exception and all those that follow it are aborted,
generally before committing any state, and can be
re-executed after servicing the exception. When following
instructions are aborted, exceptions associated with those
instructions are also aborted. Therefore, exceptions are not
taken in the order detected, but rather in instruction fetch
order.
The exception handling system is responsible for the
efficient handling of relatively infrequent events, such as
translation misses, arithmetic overflow, I/O interrupts, and
system calls. These events cause the interruption of the
normal flow of execution; aborting instructions which cause
exceptional conditions and all those which follow and have
already begun executing, and a direct jump into a
designated handler routine.
The architecture defines a minimal amount of
additional state which is saved in coprocessor registers in
order to facilitate the analysis of the cause of the exception,
the servicing of the event which caused it, and the
resumption of the original flow of execution, when
applicable.
Table 2 Exception Vectors
Exception
Type
Vector
Offset
BEV
R4300i Processor Exception Vector
32-bit mode 64-bit mode
Reset, Soft
Reset,
NMI
0x000 - 0xBFC0 0000 0xFFFF FFFF BFC0 0000
TLB Refill 0x000
0 0x8000 0000 0xFFFF FFFF 8000 0000
1 0xBFC0 0200 0xFFFF FFFF BFC0 0200
XTLB
Refill 0x080
0 0x8000 0080 0xFFFF FFFF 8000 0080
1 0xBFC0 0280 0xFFFF FFFF BFC0 0280
All Other 0x180
0 0x8000 0180 0xFFFF FFFF 8000 0180
1 0xBFC0 0380 0xFFFF FFFF BFC0 0380
Table 3 Exception Priority Order
Reset (highest priority)
Soft Reset
NMI
Address Error -- Instruction fetch
TLB Refill -- Instruction fetch
TLB Invalid -- Instruction fetch
Bus Error -- Instruction fetch
System Call
Breakpoint
Coprocessor Unusable
Reserved Instruction
Trap Instruction
Integer Overflow
Floating-point Exception
Address Error -- Data access
TLB Refill -- Data access
TLB Invalid -- Data access
TLB Modified -- Data write
Watch
Bus Error -- Data access
Interrupt
19 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
Interface Signals
The processor interface signals allow the processor to
access external resources needed to satisfy cache misses and
uncached operations, while permitting an external agent
access to some of the processor internal resources. The
signals include the System interface, the Clock/Control
interface, the Interrupt interface, the Joint Test Action
Group (JTAG) interface, and the Initialization interface.
Figure 49 illustrates the functional groupings of the
processor signals.
Figure 49 R4300i System Interface Signals
The system interface signals provide the connection
between the R4300i processor and the other components in
the system. The system interface consists of: 32-bit address
and data bus, 5-bit command bus, and multiple
handshaking signals. Table 4 lists the system interface
signals.
The clock/control interface signals make up the
interface for clocking and clock synchronization. Table 5
lists the Clock/Control interface signals.
The initialization interface signals make up the
interface by which an external agent initializes the
processor operating parameters. Table 6 lists the
initialization interface signals.
The interrupt/status interface signals make up the
interface used by the external agent to interrupt the R4300i
processor and to monitor instruction execution for the
current processor cycle. Table 7 lists the interrupt/status
interface signals.
Table 4 System Interface Signals
Name Direction Description
SysAD(31:0) Input/Ou
tput
A 32-bit address and data bus for communication
between the processor and an
external agent.
SysCmd(4:0) Input/Ou
tput
A 5-bit bus for command and data identifier
transmission between the processor
and an external agent.
EValid* Input
Signals that an external agent is driving a
valid address or valid data on the SysAD
bus.
PValid* Output Signals that the processor is driving valid
address or valid data on the SysAD bus.
EReq* Input Signals that an external agent is requesting
the system interface bus.
PReq* Output Signals that the processor is requesting
the system interface bus.
EOK* Input Signals that an external agent is capable
of accepting a processor request.
PMaster* Output Signals that the processor is the master of
the system interface bus.
SysAD(31:0)
SysCmd(4:0)
EValid*
PValid*
EReq*
PReq*
TClock
MasterClock
SyncOut
SyncIn
ColdReset*
Reset*
Int*(4:0)
NMI*
JTDI
JTDO
JTMS
JTCK
Initialization
Interface
Interrupt
System Interface
R4300i
Logic
Symbol
5
EOK*
JTAG
Interface
32
Clock and
PLLCAP0
PLLCAP1
5
PMaster*
Interface Control Interface
DivMode 1:0
TestMode
Table 5 Clock/Control Interface Signals
Name Direction Description
MasterClock Input Master clock input that establishes the
processor operating frequency.
TClock Output
Transmit clocks that establish the System
interface frequency. Tclock is aligned with
SyncIn at the MasterClock frequency.
SyncOut Output
Synchronization clock output. Must be
connected to SyncIn through an interconnect
that models the interconnect
between TClock and the external agent
aligned with MasterClock.
SyncIn Input Synchronization clock input.
DivMode
1:0* Input
These signals determine the ratio between
the MasterClock and the internal
processor PClock. DivMode 1:0 are
encoded as follows:
00 = 1:1 MasterClock to PClock ratio.
01 = 1.5:1 MasterClock to PClock ratio.
10 = 2:1 MasterClock to PClock ratio.
11 = 3:1 MasterClock to PClock ratio.
Table 6 Initialization Interface Signals
Name Direction Description
Reset* Input Used to initiate a soft reset sequence.
ColdReset* Input
When asserted, this signal indicates to the
R4300i processor that the +3.3 volt power
supply is stable and the R4300i chip
should initiate a cold reset sequence. The
assertion of ColdReset* will reset the PLL.
PLLCAP0 Input
A capacitor is connected between
PLLCAP0 and the clock VssP to insure
proper operation of the PLL.
PLLCAP1 Input
A capacitor is connected between
PLLCAP1 and the clock VccP to insure
proper operation of the PLL.
TestMode* Input
Used for cache testing. This signal must
be connected to Vcc during normal operation.
This pin will be part of the JTAG
scan chain.
Table 7 Interrupt/Status Interface Signals
Name Direction Description
Int*(4:0) Input
Five general processor interrupts. These
are visible as bits 14 to 10 of the Cause
register.
NMI* Input Non-maskable interrupt.
20 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
The JTAG interface signals make up the interface that
provides the JTAG boundary scan mechanism. Table 8 lists
the JTAG interface signals.
Figure 50 shows the primary communication paths for
the System interface: a 32-bit address and data bus,
SysAD(31:0), and a 5-bit command bus, SysCmd(4:0). These
buses are bidirectional; that is, they are driven by the
processor to issue a processor request, and by the external
agent to issue an external request.
A request through the System interface consists of: an
address, a system interface command that specifies the
precise nature of the request, and a series of data elements
if the request is for a write, or read response.
Figure 50 System Interface Bus
Cycles in which the SysAD bus contains a valid address
are called address cycles. Cycles in which the SysAD bus
contains valid data are called data cycles. The most
significant bit of the SysCmd bus is used to indicate
whether the current cycle is an address cycle or a data cycle.
During address cycles, the remainder of SysCmd contains a
system interface command. During data cycles, the
remainder of SysCmd contains the data identifier.
The processor will repeat the address cycle until the
external agent indicates that it is capable of accepting the
request. The last address cycle is called the issue cycle. There
are two types of issue cycle: processor read request issue
cycles, and processor write request issue cycles.
When the R4300i processor is driving the SysAD and
SysCmd buses, the System interface is in master state. When
the external agent is driving the SysAD and SysCmd buses,
the System interface is in slave state. The processor is the
default master of the system interface.
The external agent becomes master of the system
interface only through arbitration protocol or uncompelled
change to slave state. An uncompelled change to slave state is
initiated by the processor. There are two broad categories of
requests: processor requests and external requests. Processor
requests include: read requests, and write requests. External
requests include: read responses and write requests.
A processor request is a request through the System
interface, to access some external resource. The following
rules apply to processor requests.
• After issuing a processor read request, the
processor cannot issue a subsequent read request
until it has received a read response.
• It is possible that back-to-back write requests can
be issued by the R4300i with no idle cycles on the
bus between requests.
A Processor Read Request is issued by driving a read
command on the SysCmd bus, driving a read address on the
SysAD bus, and asserting PValid*. Only one processor read
request may be pending at a time. The processor must wait
for an external read response before starting a subsequent
read. The processor transitions to slave after the issue cycle
of the read request by de-asserting the PMaster* signal. An
external agent may then return the requested data via a read
response. The external agent, which has become master,
may issue any number of writes before sending the read
response data. An example of a processor read request and
an uncompelled change to slave state occurring as the read
request is issued is illustrated in Figure 51.
Figure 51 Processor Block Read Request Protocol
A Processor Write Request is issued by driving a write
command on the SysCmd bus, driving a write address on
the SysAD bus, and asserting PValid* for one cycle,
followed by driving the appropriate number of data
identifiers on the SysCmd bus, driving data on the SysAD
bus, and asserting PValid*. For 1- to 4-byte writes, a single
data cycle is required. Byte writes of size 5, 6, & 7 are broken
up into 2 address/data transactions; one 4 bytes in size, the
other 1, 2, or 3 bytes. For all sizes greater than 7 bytes (e.g.
8, 16, 32), 4 bytes will be sent on each data cycle until the
appropriate number of bytes have been transferred. When
the last piece of data is being transferred, this final data
cycle will be tagged as “Last Data” on the command bus.
To be fully compliant with all implementations of this
protocol, an external agent should be able to receive write
data over any number of cycles with any number of idle
Table 8 JTAG Interface Signals
Name Direction Description
JTDI Input Data is serially scanned in through this
pin.
JTCK Input
The processor receives a serial clock on
JTCK. On the rising edge of JTCK, both
JTDI and JTMS are sampled.
JTDO Output Data is serially scanned out through this
pin.
JTMS Input JTAG command signal, indicating the
incoming serial data is command data.
R4300i
External Agent
SysAD(32:0)
SysCmd(4:0) SCycle 1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus Addr
SysCmd Bus Read
PValid*
EOK*
PMaster*
21 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
cycles between any two data cycles. However, for this
implementation (i.e. R4300i) the data will begin on the cycle
immediately following the write issue cycle, and transfers
data at a programmed cycle data rate thereafter. The
processor drives data at the rate specified by the data rate
configuration signals.
Writes may be cancelled and retried with the EOK
signal.
The example in Figure 52 illustrates the bus
transactions for a two word data cache block store.
.
Figure 52 Processor Block Write Request With D Data Rate
External Write Requests are similar to a processor
single write except that the signal EValid* is asserted
instead of the signal PValid*. An external write request
consists of an external agent driving a write command on
the SysCmd bus and a write address on the SysAD bus and
asserting EValid* for one cycle, followed by driving a data
identifier on the SysCmd bus and data on the SysAD bus
and asserting EValid* for one cycle. The data identifier
associated with the data cycle must contain a last data cycle
indication. Note that the external agent must gain and
maintain bus mastership during these transactions.
An external write request example is illustrated in
Figure 53.
Figure 53 External Write Request
During An External Read Response the external agent
returns data to the processor in response to a processor read
request by waiting for the processor to transition to slave,
and then returning the data via a single data cycle or a series
of data cycles sufficient to transmit the requested data. After
the last data cycle is issued the read response is complete
and the processor will become the master (assuming EReq*
was not asserted). If at the end of the read response cycles,
EReq* has been asserted, the processor will remain slave
until the external agent relinquished the bus. When the
processor is in slave mode and needs access to the SysAD
bus, it will assert PReq* and wait until EReq* is de-asserted.
The data identifier associated with a data cycle may
indicate that the data transmitted during that cycle is
erroneous; however, an external agent must return a block
of data of the correct size regardless of erroneous data
cycles. If a read response includes one or more erroneous
data cycles, the processor will take a bus error.
Read response data must only be delivered to the
processor when a processor read request is pending. The
behavior of the processor if a read response is presented to
it when there is no processor read pending is undefined. A
processor single read request followed by a read response is
illustrated in Figure 54.
Figure 54 Single Read Followed by Read Response
Clocks
The clocks on the R4300i processor are controlled via an
on-chip Phase Locked Loop circuit. This circuit keeps the
internal clock edges aligned with the clock edges of the
MasterClock signal, which acts as the system master clock.
Inside the R4300i processor, the MasterClock signal is
multiplied by a factor determined by DivMode 1:0, and
then all internal clocks are derived by dividing that signal
down. There are two primary internal clocks, the pipeline
clock PClock, and the system interface clock SClock. While
other internal edges may be generated, these are
transparent to the user.
The pipeline clock PClock is a multiple of the
MasterClock frequency as determined by DivMode 1:0.
The system interface clock, SClock, is equal to the
MasterClock frequency.
TClock is generated by the processor at the same
frequency as SClock. It is aligned with SClock. It is used by
external agents to drive data, and as the global clock for the
external agent. TClock can be thought of as the
synchronized external system interface clock.
SCycle 1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus Addr Data0 Data1
SysCmd Bus Write Data EOD
PValid*
PMaster*
EOK*
SCycle 1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
SysCmd Bus
PValid*
PMaster*
EReq*
EValid*
Addr Data
Write EOD
SCycle 1 2 3 4 5 6 7 8 9 10 11 12
SClock
SysAD Bus
SysCmd Bus
PValid*
PMaster*
EOK*
EValid*
Addr
Read
Data
EOD
22 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
Mode Selectable Features
The R4300i processor will support several user
selectable modes, most of which can be set and reset by
writing to the CP0 Status register.
The Reduced Power (RP) mode allows the user to
change the processor operating frequency to quarter speed.
This is established by setting bit 27 of the Status register.
This feature is included to allow the user to selectively
reduce power when the system is not being heavily used.
This feature will reduce the power consumed by the
processor chip to 25% of its normal value. The default of this
mode is normal clocking. The chip will return to this state
after any reset.
The Floating-point Register (FR) mode (bit 26 of the
Status register) enables the user to access the full set of 32
64-bit floating point registers as defined in MIPS-III. When
reset, the processor will access the registers as defined in the
MIPS II architecture. This functionality is the same as the
R4000.
The Reverse Endianness (RE) mode (bit 25 of the Status
register) allows the user to switch byte ordering, between
BigEndian and LittleEndian, as seen by user software.
The Instruction Trace Support (ITS) mode allows the
user to track branches or jumps. This mode is set by writing
bit 24 of the Status register. When the ITS bit is set, the
physical address to which the CPU has branched will be
reported on the SysAD bus by forcing an instruction cache
miss whenever a branch, jump or exception is taken.
The Bootstrap Exception Vectors (BEV), bit 22 in the
Status register, when set, causes the TLB refill exception
vector to be relocated to a virtual address of 0xbfc00200 and
the general exception vector to 0xbfc00380. When cleared,
these vectors are normally located at 0x80000000 (TLB
refill), 0x00000080 (XTLB refill), and 0x80000180 (general),
respectively. This bit is used when diagnostic tests cause
exceptions to occur prior to verifying proper operation of
the cache and main memory system.
The Kernel Extended Addressing (KX), bit 7 of the Status
register, when set will enable the extended addressing TLB
refill exception vector to be used for TLB misses on kernel
addresses.
The Supervisor Extended Addressing (SX), bit 6 of the
Status register, if set, enables MIPS III opcodes in
supervisor-mode and causes TLB misses on supervisor
addresses to use the Extended TLB refill exception vector.
The User Extended Addressing (UX), bit 5 of the Status
register, if set, enables MIPS III opcodes in user-mode and
causes TLB misses on user addresses to use the Extended
TLB refill exception vector. If clear, implements MIPS II
compatibility on virtual address translation.
The Interrupt Enable (IE), bit 0 of the Status register,
when clear, will not allow interrupts with the exception of
reset and non-maskable interrupt.
LOW POWER DISSIPATION
The R4300i is carefully designed to restrict power
dissipation to make the processor suitable for operation in
battery-powered devices. Power dissipation in the R4300i is
controlled in two ways:
• Power management: The processor may be
switched into reduced-power mode or
power-down mode by external system logic.
• Reduced Power: A wide variety of logic and circuit
design techniques is used to reduce power
consumed in normal operating mode.
Power Management
The R4300i may be dynamically switched to one
quarter of its normal operating frequency by the setting
Reduce Power (RP) mode bit in the Status register. This will
slow the pipeline and processor clocks to a frequency
equivalent to one-fourth the MasterClock frequency. This
event is typically initiated by external logic which sets the
RP bit in the Status register via software. On setting this bit,
the output of the clock dividers changes to provide the
slower clock rate. Processing continues at one quarter the
rate as before. There is a corresponding drop in power
dissipated to one quarter of that previously.
The Power-down mode is typically initiated by external
logic. All dirty cache lines are written back to main memory.
All variable registers are readable and writable by software.
This allows them to be saved and written to non-volatile
memory while the processor is powered down. When
power is restored, the processor state may be written back.
State information is written using external software
routines.
Reduced Power
A variety of circuit and logic design techniques is used
to reduce power dissipation in the R4300i. Many of these
techniques save only a small amount of power but it is the
cumulative effect of these that produces a significant result.
These techniques are:
• 3.3V Power supply
• dynamic (rather than static) logic design
• unified datapath for less capacitance
• turning off unused portions of the chip
• minimized feature set
• 5-stage pipeline for high efficiency
• write-back data cache
• double instruction fetch from I-cache
• use of 2-entry micro I-TLB
• unused logic operates on constants
• gating clocks to pipeline logic to preserve data in a
pipeline stall
• Speed de-optimization (no duplicate critical paths)
• Slew rate control and optimal fanout ratios for
minimized switching current.
• Minimized Vcc to Vss current path
23 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
These all combine to produce the low average power
dissipation that allows the R4300i to be a practical
battery-powered processor.
Differences Between The R4300i And R4200
The primary differences between R4300i and the R4200
are the system interface bus architecture and the absence of
parity. The low-cost package requirements of the R4300i
necessitated a new bus definition, which is very similar to
but not the same as the R4200 system interface bus.
The functional differences between the R4200 and the
R4300i processor’s that are visible to software are contained
in the Coprocessor 0 implementation.
Table 9 gives a quick reference of the differences
between the R4300i and R4200 Microprocessors. A more
detailed description of these differences follows.
The following describes Table 9 in more detail.
The R4300i microprocessor does not provide parity
protection for the caches. The R4300i does not support
parity and will never take parity error exception.
In the R4300i the CacheErr register (register 27) in
Coprocessor0 is not implemented, hence any accesses to
this register are undefined. In addition, the PErr register
(register 26) in Coprocessor0 is used for diagnostic
purposes only. The CE and DE bits in the Status register
which are associated with parity handling are unused and
hardwired to 0 and 1 respectively.
The Configuration register fields BE and EP of the R4200
microprocessor are set by hardware to the values specified
by BigEndian and DataRate pins during reset and are read
only by software. The R4300i microprocessor sets these
fields to default values during ColdReset* and allows
software to modify them. Bits[19..18] of the Configuration
register are changed from 00 in R4200 to 01 in the R4300i.
The R4300i uses a similar System Interface protocol to
the SysAD bus protocol. The R4300i system interface bus is
32-bits and does not support parity.
Instruction blocks are written to the memory system as
a block of eight word-transactions instead of the sequence
of four doublewords separated by one dead cycle.
The fast data rate in the R4300i is D as opposed to DDx
in the R4200 Microprocessor. The data rate is software
programmable on the R4300i via the Configuration register,
whereas it is a pin on R4200.
The clock interface differs in that the R4300i does not
output MasterOut and RClock. The clock derivation scheme
in the R4300i is also different from the R4200. Instead of
always multiplying MasterClock by 2 to generate PClock,
the multiplication factor is now obtained from
DivMode(1:0) pins of the chip. This factor can be 1x, 2x, 3x
or 1.5x to give the ratios of 1:1, 2:1, 3:1 and 3:2 between
PClock and MasterClock respectively. SClock and TClock
are always the same frequency as MasterClock, instead of
being derived from PClock.
There are two sets of Vcc/Vss on R4300i. One for I/O
and core, the other for PLL. R4200 has three sets, one for
I/O, one for core and one for PLL.
The R4300i package is a 120 pin PQFP, while the R4200
uses 208 pin PQFP. The R4300i will use a 179 pin PGA as a
debug package.
The physical address of the R4300i physical address is
32 bits, while the R4200 physical address is 33 bits.
The R4300i has a four-deep flush buffer to improve
performance of back to back uncached write operations.
Each entry in the flush buffer of 100 bits (64-bits data, 32-bits
address, 4-bit size field).
Reset on the R4300i microprocessor does not need to be
asserted during or after assertion of ColdReset. ColdReset
does not need to be asserted/deasserted synchronously
with MasterClock.
When multiple entries in the TLB match during a TLB
access, the TLB will no longer shutdown and the processor
will continue operation. The TS bit in the Status register will
still be set.
The R4300i Microprocessor is housed in a 120 pin PQFP
package. The device contains only one row of pins on each
side, hence the numbering scheme is counted in a
counterclockwise fashion from 1-120. Table 10 lists the pins
and their corresponding pin name. The diagram following
shows the physical pin locations and layout of the R4300i
Microprocessor.
Table 9 Differences Between the R4200 and R4300i
Function R4200 R4300i Notes re: R4300i
Parity Support Yes No
Not
Implemented
CacheErr Register Yes No
Not
Implemented
PErr Register Yes No
Diagnostic Use
Only
Config Register
BE/EP Fields
Hardware
Controlled
Software
Controlled
Set to default
values during
ColdReset*
Config Register bit 12 Reserved Reserved
Config Register bits
[19:18]
00 01
Fast Data Rate DDx D
Software
programmable
MasterOut Signal Yes No
RClock Signal Yes No
Clock Multiplication Fixed Programmable DivMode [1:0]
Vcc/Vss Grouping 3 2
I/O and Core
the same
Packaging 208 pin PQFP 120 pin PQFP
Physical Address 33 bits 32 bits
Flush Buffers 1 4 64-bits each
R4300 Data Sheet, Rev 0.3, April 1997 24
R4300i MICROPROCESSOR
Table 10 R4300i Pin-Out
1 Vcc 31 Vss 61 Vss 91 Vcc
2 Vss 32 Vcc 62 Vcc 92 Vss
3 SysAD22 33 SysAD16 63 JTDI 93 NMI
4 SysAD21 34 SysAD15 64 SysAD4 94 SysAD26
5 Vcc 35 Vss 65 JTDO 95 PMaster*
6 Vss 36 Vcc 66 SysAD3 96 Vcc
7 SysAD20 37 SysAD14 67 Vss 97 Vss
8 Vcc 38 SysAD13 68 Vcc 98 SysAD25
9 VccP 39 Vss 69 SysAD2 99 EReq*
10 VssP 40 Vcc 70 SysAD1 100 SysCmd0
11 PLLCAP0 41 SysAD12 71 Vss 101 Vcc
12 PLLCAP1 42 SysAD11 72 Vcc 102 Vss
13 VccP 43 Vss 73 SysAD0 103 SysCmd1
14 VssP 44 Vcc 74 PReq* 104 Reset*
15 Vcc 45 SysAD10 75 Vss 105 EValid*
16 MasterClock 46 Int0* 76 Vcc 106 SysCmd2
17 Vss 47 SysAD9 77 SysAD31 107 Vcc
18 TClock 48 VsSysADs 78 PValid* 108 Vss
19 Vcc 49 Vcc 79 Vss 109 SysCmd3
20 Vss 50 SysAD8 80 Vcc 110 ColdReset*
21 SyncOut 51 SysAD7 81 SysAD30 111 SysCmd4
22 SysAD19 52 JTMS 82 EOK* 112 DivMode1
23 Vcc 53 Vss 83 SysAD29 113 Vcc
24 SyncIn 54 Vcc 84 Vss 114 Vss
25 Vss 55 SysAD6 85 Vcc 115 SysAD24
26 SysAD18 56 SysAD5 86 SysAD28 116 DivMode0
27 SysAD17 57 JTCK 87 SysAD27 117 SysAD23
28 Int4* 58 Int1* 88 Int2* 118 Int3*
29 Vcc 59 Vss 89 Vss 119 Vcc
30 Vss 60 Vcc 90 Vcc 120 Vss
R4300 Data Sheet, Rev 0.3, April 1997 25
R4300i MICROPROCESSOR
VSS
VCC
Int4*
SysAD17
SysAD18
VSS
SyncIn
VCC
SysAD19
SyncOut
VSS
VCC
TClock
VSS
MasterClock
VCC
VSSP
VCCP
PLLCap1
PLLCap0
VSSP
VCCP
VCC
SysAD20
VSS
VCC
SysAD21
SysAD22
VSS
VCC
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS
VCC
SysAD16
SysAD15
VSS
VCC
SysAD14
SysAD13
VSS
VCC
SysAD12
SysAD11
VSS
VCC
SysAD10
Int0*
SysAD9
VSS
VCC
SysAD8
SysAD7
JTMS
VSS
VCC
SysAD6
SysAD5
JTCK
Int1*
VSS
VCC
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
VSS
VCC
JTDI
SysAD4
JTDO
SysAD3
VSS
VCC
SysAD2
SysAD1
VSS
VCC
SysAD0
PReq*
VSS
VCC
SysAD31
PValid*
VSS
VCC
SysAD30
EOK*
SysAD29
VSS
VCC
SysAD28
SysAD27
Int2*
VSS
VCC
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
VCC
VSS
NMI*
SysAD26
PMaster*
VCC
VSS
SysAD25
EReq*
SysCmd0
VCC
VSS
SysCmd1
Reset*
EValid*
SysCmd2
VCC
VSS
SysCmd3
ColdReset*
SysCmd4
DivMode1
VCC
VSS
SysAD24
DivMode0
SysAD23
Int3*
VCC
VSS
26 R4300 Data Sheet, Rev 0.3, April 1997
R4300i MICROPROCESSOR
Ok... so instead of posting all of that, wouldn't it have been easier to just post the link to where you got all of that from?
Something like this maybe:
http://www.zophar.net/tech/files/N64ops03.txt
http://www.zophar.net/tech/files/n64cpu.pdf
this project is dead.
i lost all hope
thanks strmnnrmn...daedalus could've been so much more.
i heard he was attending some school in Europe........probably not true though
If you want 1 link psp games also known as ISOS and roms from various systems come to my profile =]
austiniso, nice game list! =D
@charles
I deleted Daedalus off my MacBook a long time ago!
but here is the source
http://www.68kshrine.net/temp/DaedalusR14Source.zip
Cheers
Wally
P.S guys, StrmnNrmn has a history for not updating blogs and leaving projects for the dead so yeah.
What a shame.
Well it may have been left for dead, but I might see fit for a resurrection, if life slows down a bit and I can find the time. Oh, well. Everyone will probably have to wait for sometime in September for that. I will post again if I ever get started on it. If not, sorry it was fun though.
What needs to happen with all the emulators out there is to create a new version of tweaks made specifically for each game. Make a copy of the same emu, but with tweaks related only to one game and optimize it to the max. Then move on to the next.
Essentially we would then have Daedalus-Mario edition, Daedalus-Ocarina of time edition. Etc. etc.
Trying to create one emu that emulates all perfectly seems to be spreading the project too thin.
Do a poll, pick the five most popular and create a version for each and then call it quits. There are only a few games we want to play.
What Happened Man. Ive hardly heard A Thing about you, this was the betterof the two emulators and now I've been waiting for an update for ages.
What Happened?
As was was hoping life has slowed down. I've gotten permission to use code from some PC N64 emulators. I'm going to contrast and compare to see what I think will work best. First off, I'm going to go in this order:
1.Comb through all the code I have while learning about PSP programming.(My experience is with the PC.) (Hopefully the Daedalus code at the open source project will be updated to the latest SVN...)
2. Begin combining code with one priority. Mario64 Full speed and effects.
3. Next the Zelda titles and then Perfect Dark.
4.Then Mario Cart and Pokemon Puzzle League)
Why? Mario is closest to finished. I have access to the hardware and carts for the others and I'm doing it and I like them.
dear Charles,
best of luck!
i am very interested to see how this goes, and i now have an excuse to check this blog for updates...to YOUR project!
@Charles
That sounds great!
I wish you good luck with your project.
Maybe you should start your own blog and post updates and such there?
/Peter
Charles,
If you are who you say you are best of luck and ill be looking forward to be seeing what you can do....the Project has come to far to just die
Sorry to bring you the bad news guys. Strmnnrmn is dead. There wont be any more new updates. We will miss you strmnn Rest in Peace! You were the man...
LOL Randy you're a complete idiot.
You're just a sad attempt at trying to get shit stirred up and trying to get into news on all the sites.
You deserve to die, seriously :)
300!
301!
302!
303!
Buenas, soy español y no entiendo mucho de inglés, quisiera saber si se ha dado alguna noticia de alguna actualización o algo parecido o si se ha cancelado el proyecto o algo parecido, me disculpo por mis palabras en castellano pero si alguien que sepa español me informa se lo agradecería, un saludo.
No ha habido noticias para las edades como se puede ver, oído nada de strmnnrmn, el proyecto está al parecer desde hace mucho tiempo muerto, tú a alguien en estos comentarios reclamaciones que empezar a trabajar en este proyecto en lugar de strmnrmn pero no recibe su espera.
No espero mucho de Daedalus. Es muy poco probable cualquier cosa grande que va a suceder, pero que sabe.
Por cierto i utilizado un traductor de este mensaje por lo que no podría hacer perfecto sentido
Thanks swish.
Bueno, lo que te ha venido a decir es que el proyecto como ves está muerto desde Navidades del año pasado. No se ha sabido nada de su autor (strmnnrmn) desde entonces. Lo único fue que se descubrió como una beta en la que estaba trabajando Strmnnrmn hace tiempo, la publicó un tal Wally. Entonces se empezó a especular de si Strmnnrmn posteaba bajo un pseudónimo y cosas así, pero nada en claro. En la página www.strmnnrmn.com podrás encontrar dicha beta. Creo que estaba en código claro y se dijo que si habría gente que lo cogería, pero otra vez nada en claro. Un tal charles dijo hace poco que quizás retomara el proyecto, pero como vengo repitiendo, nada está claro. Saludos.
@Charles
Best of luck to you good sir.
Make sure to make a blog and update us on your progress as you feel necessary.
When your ready, send an email to QJ, digg, DCEmu, et al. and the followers will start flowing in.
Gracias josep a ti también por la información, no tenía ni idea
@John
If you see comments above a LONG time ago, before you posted,i said this "Blogger Framework said...
I have an Idea to get Paper Mario running. If you can boot up a save after you write the name you want in the game then it might work.The save could probably have the name Mario cuz no one will care. Problem is...Where can i find a Paper Mario .sav?"
AND I DONT EVEM GET ANY REPLY or thanks for my suggestion ;____;
thats cause it didnt work bitch
and if you still want that save just make one on the compy on an emu.
I don't exactly understand the progress of coding an Emulator for the N64 on the PSP, but shouldn't this run very well, because both consoles use a MIPS CPU? And what exactly has to be optimized from the PC-based emulators?
Thanks for info.
Sorry guy, but the moment things slow down and a get a moment to start comparing sources. Then it all gets messed up again. I probably won't respond to this blog except once more. (Which will be a progress update and will setup some sort of hosting for my own development blog.) If Strmnnrmn does pick this back up I will make should I heavily comment the code and see if we can't make things run smoother together with more frequent updates. (I have another project I'm also working on, so it will probably be around Christmas for that first update.)
Yeah over at StrmnNrmn.com we have a new Dev there that is picking up from Daedalus R-14beta and has some nice plans already, details there.
Interesting.
Maybe sticking around over 10 months after Strmnnrmn left wasn't a waste of time after all lol.
Yay this is great news!
When is is released go here, for a compatibility list
A comment was deleted by the author ?
I assume Strmnnrmn isn't the only one who can delete comments.
that last deleted comment raises some suspicion?!?
The fact that the project is being continued is great, but the fact that they're not using the artwork chosen for Daedalus last year is pretty disappointing. You'd think they'd show the original project at least that much respect.
I doubt Strmnnrmn would hang around for like 9+ months and just view the comments lol.
It's surprising that someone with the authority to delete comments is still hanging around.
Anyone can delete their own comment. Look at the trash can icon under your posts.
Whoa. Heavy duty irony there, Swish :)
This is the post he deleted:
"But it says the post has been deleted by the author.
It wouldn't say that if you were to delete your own comment."
After i made the comment i realized what he was talking about, so the only way i could see if it was right or not was to delete my comment, i wanted to make another comment after that but it wouldn't let me.
But yeah it's good to know.
For some reason I have a feeling Strmnnrmn is just gona pop outta nowhere in xmas and give us all a heck of an update. Just my 2 cents. Probably not going to happen.
Sounds like wishful thinking :P
Even if he did, what are the odds of him coming back and doing a lot of work.
At this point anything is better then nothing thou.
I think he should have at least made some kind of good bye post.
maybe his computer crashed and lost all his hard work, then got so angry that he abandoned internet.
i don't know...
it could happen 0.o
maybe he got hit by a bus.
could've happened.
maybe those mince pies poisoned him.
could've happened.
that has got to be the 11th time that mince pie joke has been used in these comments
i wasn't paying attention.
you counted?!
maybe he choked on those mince pies.
could've happened.
12
haha no i haven't counted. i was exaggerating. it is a joke that has been used many times, 'tis all
http://pspupdates.qj.net/More-DaedalusX64-screens-GoldenEye-007-Ocarina-of-Time-back-up-to-R13-speeds/pg/49/aid/125984
maybe he's still watching The Great Escape on tv. a year long marathon. could've happened.
new joke (i think)
I said I would help restart this project and I have. Also thx to Wally, Chilly Willy (AKA J.F), hlide, and howard0su for helping out and being part of the team.
Check out:
Official Forum @
http://daedalusx64.com/index.php
Release Site @
https://sourceforge.net/projects/daedalusx64/
DaedalusX64 is now in public beta test.
BTW: I'm the charles who posted above about restarting this.
Go to http://www.Myspace.com/DaedalusPspCompatibility for a list of updated compatibility on Daedalusx64.
Hey Yall!
(wow i cant believe that this forum has lasted this long!!!)
i was just writing the comment to tell yall that i personally admire all of you. you all have stuck with the project for a year after it's "death." And i consider yall to be the real fans, and hard core Daedalus supporters.
@ Wally: I believe i ow you an apology. i left a rather nasty comment about your credibility earlier, so I am sorry. I hope you read this even though you probably don't ever check this blog anymore. sorry.
@ Framework: Hey dude thanks for the suggestion, but i kinda already tried it. i poster a reply a good while ago explaining what the problems were, and why i didn't think that my original plan would ever work (without an emulator update, that is), you probably didn't see it though. but thanks anyway. Also i want to apologize for Robbie's comment, it was kinda un-called for, so sorry.
I personally want to thank everyone who has helped to bring the project back to life (the Daedalusx64 team).
@ Everyone: i really liked Swish's comment and i think that we should all, as a group, us hard-core fans, put our brains together to make a Strmnnrmn memorial. i was tossing around the idea for about half a year or so, then for no real reason, i came and checked this blog again, and my thoughts were re-sturred (i guess), so yea.
what i had in mind was that you (everyone who still checks this blog), could send emails to this email address, with your ideas on what the memorial should be/look/say etc.
i own Adobe Photoshop, and a Wacom tablet, and i am more than happy to do an artistic memorial for strmnnrmn. i consider myself a good artiest, and i would like to gather up all of your email comments regarding the memorial and put them together into one big image commemorating the work that Strmnnrmn did. (and maby still is doing, but i kinda doubt it. no offense of course.)
my only concern is that other people will have the same idea, and a bunch of different people will go off and try to make different strmnnrmn memorials. i'm not saying that that is a bad idea, but i simply feel that if we are going to have a real memorial for strmnnrmn, then we should only have one and it should come from all of us. (i'm not trying to hog the memorial to myself, but i am taking the first step in organizing one.)
if yall want to check out some of my work (artistic work) then you can go to my profile page at DeviantArt. just click on the "Gallery" button at the far right to see all of my work. and my user name for that site is (yes i will say it) Shock-Socks.
here's the link:
http://shock-socks.deviantart.com/
and here's the email address that you can use to send me emails regarding the memorial:
strmnnrmn.memorial.project@gmail.com
so yeah (this post is far too long >_<)
please help to make this idea a reality, and if there are other artists that see this, maby yall can help too.
see yall later!
P.S. you guys..... this has gone on for far to long.
when there is a comment that says:
"Comment deleted
This post has been removed by the author."
it means that the AUTHOR of the comment deleted it him/her self.
no one is behind the scenes controlling what ppl say on this blog.
once again.
the AUTHOR (that means writer) of the comment is one who is deleting the comment. so for all of those deleted comments, they were not deleted by Strmnnrmn, they were deleted by their authors.
That issue was actually resolved awhile back lol.
The whole memorial thing isn't that bad of an idea, thou it's too bad Strmnnrmn probably wont be able to see it.
@ John
those are some bad ass drawings. your dragons kick ass! i draw too, but lately i haven't done anything quite as detailed.
@All
Strmnnrmn isn't dead.(Yes, I know this for a fact.) He's just moved on to bigger and better things and has a very busy life. He may come back one day, but if he does it will be his choosing. No amount of begging, pleading or anything else will make it happen sooner. However knowing what I do about him a good idea would be to give to a charity, that is memorial enough for his work. Enough said about that. The project is continuing, but the new name is out of respect for the original author.
I have 2 game saves in DX64 that I feel like sharing.
1) Mario 64 (all 120 stars)
2) Goldeneye (3 levels unlocked)
http://www.sendspace.com/file/7imkoj
>have fun<
strmnnrmn is back!!! wooot! cant wait to c you in action... we all missed you!
What on earth are you talking about, Elias?
strmnnrmn joined the DX64 team. he's back!
I'm happy your back StrmnNrmn please update you blog =D
He's still very busy and just hasn't had the time yet, but I expect an update by Christmas.
Finally!
A blog worth reading on forward until the end! :) I really admire the wording in this blog, quite precise to the details but I just might change one or two things, never-the-less, bravo on well choiced words mate.. p.s.>> Thanks for sharing, I actually picked up some knowledge on this one :)
-Have an amazing day!
Marine Engine Parts
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